Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-06-16
2002-05-28
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S145000, C711S146000
Reexamination Certificate
active
06397304
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to computers in general. In particular, the invention relates to a method and apparatus for improving system performance in multiprocessor systems by expanding the type of data available for implicit writebacks.
BACKGROUND OF THE INVENTION
In a shared memory multiprocessor system, data necessary for one processor is often present in a cache of another processor. It is more efficient to retrieve such data from the cache rather than memory. Furthermore, the system must ensure that a request for data (e.g., by a processor or input/output device) is answered with the most current version of the data available. Therefore, the system processes a request for data by first attempting to retrieve the requested data from a processor's internal cache before going to main memory.
In conventional multiprocessor systems, a request for data is originated by a first processor. The other processors detect the data request and ascertain whether they have the requested data in one of their internal caches (“snoop phase”). If the requested data is present, the processor provides the requested data on a bus for transport to the first processor (“data phase”). This entire process is typically governed by a particular bus protocol for the system, and is generally referred to as an “implicit write back” scheme.
In addition to determining whether the requested data is present in a processor's internal cache, the cache system of the processor must determine the state of the requested data. For example, in a system using the Modified/Exclusive/Shared/Invalid (MESI) cache protocol, the requested data can be in one of four states: Modified (M); Exclusive (E); Shared (S); and Invalid (I). The M state indicates that the data within a cache has been modified relative to the same data stored in main memory. Further, both the M and E states indicate that only one processor in the multiprocessor system owns the requested data. The S state indicates that multiple processors own the data. Finally, the I state indicates that the line is invalid (i.e., the cache does not have a copy of the data).
Conventional implicit write back schemes, however, may be less than satisfactory for a number of reasons. For example, if the requested data that one processor wants to read is present in the M state in another processor's cache, that processor is required to provide the requested data on the bus. If any of the processor's have the data in the S or E state, however, the data is not provided from the processor's cache, but rather it is read from memory. This introduces latency into the data retrieval process, since it is slower to retrieve data from memory than from a cache. Moreover, retrieval from memory may unnecessarily occupy limited main memory bandwidth since other caches contain the requested data.
In view of the foregoing, it can be appreciated that a substantial need exists for a method and apparatus that solves the above-discussed problems.
SUMMARY OF THE INVENTION
One embodiment of the invention comprises a method and apparatus to retrieve data for a multiprocessor system. A request for data is received at a first processor from a bus. A cache is searched for the data, with the data having a state. A determination is made as to whether the state is an exclusive state or shared state. The data is sent to the bus in accordance with the determination.
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Intel Corporation
Thai Tuan V.
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