Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – Small lead frame for connecting a large lead frame to a...
Reexamination Certificate
2000-02-10
2002-05-28
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
Small lead frame for connecting a large lead frame to a...
C257S666000, C257S668000, C438S123000
Reexamination Certificate
active
06396132
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of electronic semiconductor devices, and, more particularly, to a process for manufacturing electronic semiconductor devices.
BACKGROUND OF THE INVENTION
As is known, integrated circuits are formed on chips of semiconductor material which require, for their connection to external electrical circuits, suitable supporting, containing and electrical interconnection structures. A typical structure suitable for the purpose is enclosed in a plastic body and comprises a chip which is fixed to a flat support and is connected, by wires soldered to suitable metallized areas (pads) provided on its surface, to the ends, located inside the plastic body, of corresponding electrical conductors emerging from the body.
For the manufacture of these structures, the chip is fixed on a supporting element, for example by gluing with a suitable adhesive. Then a set of metal strips, joined together by interconnecting sections to form a frame (lead frame), is prepared and placed around the chip. The metal strips, which are designed to become the terminal conductors of the device, are formed, usually by punching, from a sheet of metal. Thin wires, usually made from gold, are soldered at one end to the metallized areas of the chip and at the other end to the ends of the metallic strips. The resulting structure, together with other identical structures connected together for serial production, is mounted in a suitable press mold into which a thermosetting epoxy resin in the liquid state is poured. The polymerization of the resin produces a structure which comprises a solid plastic body which incorporates the elements described above, with the exception of part of the metal strips, in other words of the terminal conductors of the device, and of the interconnecting sections between them. These sections are then removed by punching to produce the finished electronic device.
It is known that an increase in the integration density is accompanied by an increase in the number of terminals of the integrated circuit to be connected to the exterior. It is therefore desirable to reduce the size of the strips of sheet metal designed to form the terminals of the device, so that their density can be increased. The minimum limit for size of the strips is determined by the thickness of the sheet metal, which, moreover, cannot be less than a minimum value imposed by the necessity of providing a certain degree of rigidity, and by the requirements of the punching operation or of other cutting operations. It is also desirable to shape the strips in such a way that their ends are as close as possible to the chip but do not interfere with each other. Some of the strips are therefore made in the form of curves or bent lines. However, this requires longer and less rigid strips, and therefore entails greater difficulties in the operations of soldering the wires and greater risks of short circuit between the strips or between the wires.
Additionally, the connecting wires extend in the form of an arc in a direction perpendicular to the plane of the chip, and the height of the arc increases with the length of the wire (evidently within the practical limits of the application of this connection method) and therefore the thickness of the plastic body cannot be less than the minimum value necessary to cover the wire completely. Moreover, a frame of strips shaped in such a way as to be most suitable for use with a chip of given dimensions and with a given arrangement of the metallized areas cannot generally be used with chips having different dimensions and different arrangements of metallized areas. This causes a considerable increase in manufacturing costs, since a suitable lead frame must be designed and manufactured for each device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a device which is easily and economically manufactured and has a structure such that the prior art connection problems mentioned above are reduced, and a process for manufacturing this device.
This object is achieved according to the invention by providing a chip of semiconductor material fixed to a supporting area of a film of insulating material. Electrical interconnecting elements join metallized areas of the chip to the ends of metal strips which form the terminals of the device. To obtain devices with numerous terminals without approaching the dimensional limits imposed by the manufacture of the terminal frames, the interconnecting elements include electrically conductive tracks formed on the film of insulating material. The electrical connection between the ends of the terminals and the tracks is made by strips of anisotropic conductive material.
REFERENCES:
patent: 3544857 (1970-12-01), Byrne et al.
patent: 4110838 (1978-08-01), Noe
patent: 5874773 (1999-02-01), Terada et al.
patent: 5945729 (1999-08-01), Stroupe
patent: 0 435 093 (1990-12-01), None
patent: 408124957 (1996-05-01), None
“Chip Attachment to Tape and Cable”, IBM Technical Disclosure Bulletin, vol. 25, No. 4, Sep. 1982, pp. 1954-1956.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Flynn Nathan
Jorgenson Lisa K.
STMicroelectronics S.r.l.
Wilson Scott R.
LandOfFree
Semiconductor device with improved interconnections between... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device with improved interconnections between..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with improved interconnections between... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2909481