Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-06-12
2002-05-07
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06385760
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit design tools. In particular, the present invention relates to design tools that optimize area and performance for integrated circuits.
2. Discussion of the Related Art
The interconnection wiring (“interconnect”) among circuit elements in an integrated circuit is expected to dominate signal delays and to limit achievable circuit density of an integrated circuit. Existing design methods, which treat interconnect as “parasitics” and focus on optimizing transistors and logic gates, are ill-equipped to provide a design which delivers the necessary performance. Typically, in a conventional design method, the circuit elements of an integrated circuit are first synthesized and placed. A global routing tool is then used to interconnect these circuit elements. Because placement and routing are performed relatively independently, even though some tools take into consideration the connectivity among circuit elements in providing the placement, the global routing tool's ability to address power, timing and congestion issues is severely limited.
Concurrent placement and wiring routing is disclosed in U.S. Pat. No. 4,593,363, entitled “Simultaneous Placement and Wiring for VLSI Chips” to Burstein et al. The '363 patent discloses an iterative method in which a global router is invoked to route networks redistributed under a hierarchical placement algorithm.
SUMMARY OF THE INVENTION
The present invention provides a method and a design tool for designing integrated circuits with emphasis on circuit performance. One method of the present invention pertains to a placement algorithm for placing circuit elements onto a target area of a semiconductor substrate according to the following steps: (a) providing an initial placement of the circuit elements onto a target area; (b) providing, for each of the nets interconnecting the circuit elements, a probabilistic model of interconnect wiring based on required performance for the net; (c) optimizing the cost function associated with the placement of the circuit elements and the corresponding wiring using an iterative placement algorithm; (d) updating the performance estimations during placement to facilitate continuous adjustments of the probabilistic wiring model. Thus, in a method of the present invention, the probabilistic model of interconnect wiring are provided according to performance requirements which are updated continuously.
The placement tool optimizes gate placement using timing estimates based on a probabilistic wiring model. The wiring model represents the local, probabilistic wiring density based on the continuously updated criticality of the net. The probabilistic wiring model represents nets based on where the wiring should be routed to attain the necessary performance. The placement optimization then modifies the placement to achieve aggregate wiring that is globally feasible. The present invention can be practiced in conjunction with any placement tool which is based on iterative improvement.
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Boyle Douglas B.
Gao Tong
Pileggi Lawrence
Sarrafzadeh Majid
Taraporevala Feroze Peshotan
Garbowski Leigh Marie
Monterey Design Systems, Inc.
Vierra Magen Marcus Harmon & DeNiro LLP
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