Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-18
2002-07-16
Booth, Richard (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S330000
Reexamination Certificate
active
06420751
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to a vertical surround gate metal-oxide semiconductor field-effect transistor (hereinafter referred to as “MOSFET”). The present invention further relates to a dynamic random access memory, an inverter circuit, and a static random access memory using such a vertical surround gate MOSFET. The present invention also relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
FIG. 101
is a schematic diagram of a conventional planar type MOSFET. Referring to
FIG. 101
, a gate electrode
3
is provided on a P-type silicon substrate
1
with a gate insulating film
4
interposed therebetween. N-type source/drain regions
6
a,
6
b
are provided on both sides of gate electrode
3
in the main surface of silicon substrate
1
.
Operation of the conventional MOSFET will now be described. When a positive potential is applied to gate electrode
3
, the following reaction occurs in the main surface of silicon substrate
1
B→B
−
+h
+
where B is boron, B
−
is a boron anion, and h
+
is a hole.
More specifically, when a positive potential is applied to gate electrode
3
, boron is separated into boron anions and holes. Boron anions are attracted to gate electrode
3
. On the other hand, holes repulse gate electrode
3
to escape in silicon substrate
1
, which in turn generates a depletion layer
17
in the main surface of a channel region of silicon substrate
1
. Depletion layer
17
is a region where neither electrons nor holes exist, that is, where no carriers serving to make a current flow exist.
As a positive potential applied to gate electrode
3
is increased, depletion layer
17
is enlarged and its width Wd is increased. However, increase of the width Wd of depletion layer
17
is limited. The width of depletion layer
17
is determined by an impurity concentration. The larger the impurity concentration, the narrower the width Wd of the depletion layer. The smaller the impurity concentration, the wider the width Wd. The maximum value of the width Wd of depletion layer
17
is called maximum depletion layer width.
When the width Wd of depletion layer
17
reaches the maximum depletion layer width, an inversion layer
18
is formed on the surface of the channel region, rendering source
6
a
/drain
6
b
conductive.
When the integration density of a semiconductor device is increased, an area occupied by the MOSFET needs to be small.
FIG. 102
is a perspective view extracting and illustrating main portions of the conventional vertical type surround gate MOSFET improved so that an area occupied by the MOSFET may be made small.
Referring to
FIG. 102
, gate electrode
3
surrounds a plug-shaped silicon
5
with gate insulating film
4
interposed therebetween. Source region
6
a
is provided at an upper end of plug-shaped silicon
5
, and drain region
6
b
is provided at a lower end thereof. Drain region
6
b
is formed in the main surface of the silicon substrate.
Aluminum interconnections
10
a,
10
b,
and
10
c
are connected to source region
6
a,
gate electrode
3
, and drain region
6
b,
respectively.
When a positive potential is applied to gate electrode
3
, an inversion layer is generated on the sidewall surface of the plug-shaped silicon, causing a current to flow from source region
6
a
to drain region
6
b.
In other words, the current flows in the direction perpendicular to the silicon substrate.
Comparison is now made between an area occupied by the planar type MOSFET and an area occupied by the vertical type surround gate MOSFET.
Let L be a gate length of the planar type MOSFET, and W be a channel width of the planar type MOSFET, referring to
FIG. 101
, an occupied area Splanar of the channel region is
S
planar=
L·W
On the other hand, in the case of the vertical type surround gate MOSFET, referring to
FIG. 103
(which is a simplification of FIG.
102
), when the radius of the channel region is R, the channel width W is 2&pgr;R. An occupied area of the channel region is
S
vertical=&pgr;
R
2
=W
2
/4&pgr;
Therefore, when transistors having the gate length L equal to the channel width W are formed of a planar type MOSFET and a vertical type surround gate MOSFET, respectively, the ratio of respective occupied areas is
S
vertical/
S
planar=¼&pgr;
More specifically, an occupied area of the vertical type surround gate MOSFET is {fraction (1/12)} or less of that of the planar type MOSFET.
If occupied areas of both the vertical type surround gate MOSFET and the planar type MOSFET are made equal, it is possible to increase W in the vertical type surround gate MOSFET. This is a first advantage of the vertical type surround gate MOSFET.
Referring to
FIGS. 102 and 103
, in the vertical type surround gate MOSFET, it is possible to deplete the entire channel by decreasing the radius of channel plug
5
. Therefore, the vertical type surround gate MOSFET has advantages the same as those of a conventional SOI (Silicon-On-Insulator) MOSFET. Detailed description thereof will be given hereinafter.
If the entire channel can be depleted, it is possible to suppress a subthreshold current (a leakage current in a weakly inverted state), which in turn improves a circuit characteristic.
A subthreshold coefficient S is expressed by the following expression:
S
=ln10
·kT/q·
(1
+Cd/Cox
)
where k is a Boltzmann constant, T is an absolute temperature, q is an elementary electric charge, Cd is a depletion layer capacitance of the MOSFET, and Cox is a gate insulating film capacitance.
As is clear from the above equation, when Cd=0 holds, the subthreshold coefficient S takes the minimum value
(ln10
·kT/q
=60 mV/
dec
).
FIG. 104
is a cross-sectional view of an SOIMOSFET. An SIO layer
15
is formed on a buried oxide film
16
. Gate electrode
3
is formed on SOI layer
15
with gate insulating film
4
interposed therebetween. Source/drain regions
6
a,
6
b
are formed on both sides of gate electrode
3
in the surface of SOI layer
15
. In the figure, Wd is a depletion layer width, t
SOI
is the film thickness of SOI layer
15
, and t
BOX
is the film thickness of buried oxide film
16
.
When the entire SOI layer
15
is not depleted (that is, when Wd<t
SOI
holds), the depletion layer capacitance Cd of the SOIMOSFET is, similar to the case of the MOSFET shown in
FIG. 101
, expressed by the following equation:
Cd=&egr;
si
/Wd
On the other hand, when the film thickness of buried oxide film
16
is sufficiently larger than that of SOI layer
15
(t
Box
>>t
SOI
), and the entire SOI layer
15
is depleted (when it is in a fully depleted state, Wd≧t
SOI
), the depletion layer capacitance Cd is substantially 0. In the case of the SOIMOSFET, it is possible to make the depletion layer capacitance Cd zero by adjusting the film thickness of SOI layer
15
, thereby suppressing a subthreshold current.
The above-described advantage of the SOIMOSFET can be implemented in the vertical type surround gate MOSFET. More specifically, when the fully depleted state is implemented in the vertical type surround gate MOSFET, the depletion layer capacitance Cd is 0 similar to the case of the SOIMOSFET. Since electric power lines extend in the radial direction, the phenomenon of which is unique to the surround type MOSFET, the depletion layer capacitance Cd is smaller than that of the MOSFET shown in
FIG. 101
even in the state of incomplete depletion.
The following equation shows the relation between the radius R and the depletion layer capacitance Cd of the vertical type surround gate MOSFET, and
FIG. 105
shows the equation in the form of graph.
Cd
=
ϵ
Si
R
·
ln
(
R
/
R
-
Wd
)
)
When R/Wd<1 holds, complete depletion of the channel can be implemented. Therefore, the depletion layer capacitance Cd is 0. Even if R/Wd>1 holds, the depletion layer capacitance Cd is smaller than
Kuriyama Hirotada
Maeda Shigenobu
Maegawa Shigeto
Yamaguchi Yasuo
Booth Richard
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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