Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-07-31
2002-09-17
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S378000, C257S335000
Reexamination Certificate
active
06452231
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, more particularly, a semiconductor device having a lateral MOSFET.
Hitherto, as a switching semiconductor device with a low breakdown voltage of about 8V to 60V, lateral MOSFET is known.
FIG. 1
is a plan view showing the structure of this type of lateral MOSFET, and
FIG. 2
is a sectional view taken along the line
2
—
2
in FIG.
1
and seen in the direction indicated by arrows. This type of lateral MOSFET is constituted in such a manner that, on the surface of a p-type semiconductor substrate
1
, a p-type well layer
2
is selectively formed, and, on the p-type well layer
2
, an n-type drain layer
3
is selectively formed. On the p-type well layer
2
, an n-type source layer
4
is formed at a position spaced apart from the n-type drain layer
3
.
On that portion of the p-type well layer
2
which lies between the n-type drain layer
3
and the n-type source layer
4
, a gate insulation film
5
is formed. On the gate insulation film
5
, a gate electrode
6
is formed. On the n-type drain layer
3
, a drain electrode
7
is formed. On the p-type well layer
2
and the n-type source layer
4
, a source electrode
8
is formed.
This lateral MOSFET operates as follows:
If, when a positive voltage is applied to the drain electrode
7
and a negative voltage is applied to the source electrode
8
, a positive voltage which is more positive than the voltage at the source is applied to the gate electrode
6
, then that surface portion of the p-type well layer
2
which is adjacent to the gate insulation film
5
is inverted into the n conductivity type, and thus, electrons flow from the n-type source layer
4
to the n-type drain layer
3
through the inversion layer. That is, the element is brought into conduction.
In case such a lateral MOSFET is used for the switching of a large current, it is important in view of suppressing the loss to hold down the resistance (ON resistance) in the ON state of the lateral MOSFET. Here, the ON resistance of the lateral MOSFET is, for the most part, the resistance of the channel portion. Due to this, in order to decrease the ON resistance of the lateral MOSFET, the width of the channel thereof should be enlarged. However, if the channel width is enlarged, the area occupied by the lateral MOSFET is increased.
Further, in the case of a lateral MOSFET having a low breakdown voltage of, e.g. 30V, the ON resistance thereof is about 40 &OHgr;·mm
2
; and, any further decrease of the ON resistance has its limit.
As has been described above, in the case of a lateral MOSFET, there is the problem that, if the channel width is widened, the area occupied by the element is increased.
Further, in the case of a lateral MOSFET, current flows through only the surface thereof; and thus, there is a limit to the reduction of the ON resistance thereof.
BRIEF SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor device constituted in such a manner that the ON resistance thereof can be reduced to a substantial degree without increasing the area occupied by the element.
A lateral semiconductor device according to a first aspect of the invention is characterized by comprising an active region; a base region of a first conductivity type formed in the active region; a source region of a second conductivity type formed in the base region; a drift region of the second conductivity type formed in the active region; a drain region of the second conductivity type formed in the drift region; a plurality of trenches formed between the source and drift regions; and a gate electrode formed in the trenches.
Thus, according to the first aspect, the above-described means are adapted, so that the width of the channel can be widened, with the element's area kept the same, in accordance with the depth and the mounting density of the trenches: and therefore, the resistance of the channel portion of the element can be decreased, that is, the resistance of the element itself can be decreased, whereby the ON resistance thereof can be decreased.
Further, the device according to the first aspect may include an insulation layer formed under the gate electrode; and the gate electrode having a portion formed over the drift region and extended toward the drain region; wherein a thickness of the insulation layer under the portion is greater than a thickness of the insulation layer formed over a portion of the active region between the trenches.
Further, the device according to in the first aspect, the drain region may be formed substantially deeper than the source region. In addition, the device may include a buried electrode connected to the drain region.
Further, the device according to the first aspect may include a buried region of the second conductivity type formed in contact with the drain region and extending toward the base region. In addition, the buried region may have a higher conductivity than the active region.
Further, the device according to the first aspect may include a doped region of the second conductivity type formed in a surface region of the active region and connected to the drift region and extending between the base region and the drift region. In addition, the doped region may have a conductivity higher than the active region and lower than the drift region.
Further, the device according to the first aspect may include an interval between adjacent ones of the trenches being no greater than 0.8 &mgr;m, preferably no greater than 0.1 &mgr;m.
Further, the device according to the first aspect may include a channel region formed along the surfaces of the trenches.
A semiconductor device comprising a lateral MOSFET and bipolar, transistor according to a second aspect of the invention is characterized in that, the lateral MOSFET including: a first active region; a first base region of a first conductivity type formed in the first active region; a source region of a second conductivity type formed in the first base region; a drain region formed in the first active region; a plurality of trenches formed between the source and drain regions; a gate electrode formed in the trenches and over portions of the first active region disposed between the trenches; and a first buried region of the second conductivity type formed in contact with the drain region and extending toward the first base region; the bipolar transistor including: a second active region; a collector region of a second conductivity type formed in the second active region; a second base region of a first conductivity type formed on the collector region; an emitter region of a second conductivity type formed on the second base region; and a second buried region of the second conductivity type formed in the second active region under the collector region; wherein the first and second buried region are formed substantially with the same thickness and the same depth and the same concentration of a conductive impurity.
Thus, according to the second aspect, the above-described means are adapted, so that, by the first and second buried regions are formed substantially with the same thickness and the same depth and the same concentration of a conductive impurity, the first buried region of the lateral MOSFET and the second buried layer of the bipolar transistor can be formed by one and the same manufacturing step, so that the number of manufacturing steps can be reduced.
Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention.
The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4393391 (1983-07-01), Blanchard
patent: 5796125 (1998-08-01), Matsudai et al.
patent: 5844275 (1998-12-01), Kitamura et al.
patent: 6316807 (2001-11-01), Fujishima et al.
patent: 4-93081 (1992-03-01), None
patent: 8-
Kawaguchi Yusuke
Nakagawa Akio
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Prenty Mark V.
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