Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2000-10-05
2002-06-04
Wille, Douglas (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S149000, C438S471000, C438S592000
Reexamination Certificate
active
06399460
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a semiconductor device using a SOI (Silicon On Insulator) substrate, and a manufacturing method thereof.
2. Description of the Background Art
Semiconductor devices using a SOI substrate can reduce the junction capacitance in source/drain regions and also reduce a substrate bias effect. This leads to a high speed operation and a reduction in power consumption. Further, in semiconductor devices using a SOI substrate, a semiconductor element and a substrate are mutually isolated by the presence of an insulating layer, resulting in high resistance to soft error and high resistance to substrate noise. This enables to increase the reliability of the semiconductor devices. With the miniaturization of semiconductor devices in recent years, it seems difficult to improve various performances of semiconductor devices using a bulk substrate. Therefore, it is estimated that semiconductor devices using a SOI substrate play a dominated role in the device structure in the future.
FIG. 19
is a cross section of the structure of a conventional semiconductor device
100
using a SOI substrate. The semiconductor device
100
comprises a SOI substrate
101
having a stacked structure in which a silicon substrate
102
, buried oxide film
103
, and SOI layer
104
are stacked in this order. The semiconductor device
100
further comprises a MOS transistor
110
disposed in an element formation region of the SOI substrate
101
. The MOS transistor
110
has a channel formation region
105
selectively disposed in a main surface of the SOI layer
104
, a gate insulating film
106
on the channel formation region
105
, a gate electrode
107
on the gate insulating film
106
, and a drain region
108
and a source region
109
disposed in the main surface of the SOI layer
104
and adjacent the channel formation region
105
.
The semiconductor device
100
further comprises an element isolation insulating film
111
disposed in the main surface of the SOI layer
104
in an element isolation region of the SOI substrate
101
, and an interlayer insulating film
112
disposed on the MOS transistor
110
and on the element isolation insulating film
111
. In addition, the semiconductor device
100
includes a contact hole
113
being filled with a conductor and extending through the interlayer insulating film
112
between an upper surface of the interlayer insulating film
112
and an upper surface of the drain region
108
; a drain wiring
114
disposed on part of the upper surface of the interlayer insulating film
112
where the contact hole
113
is disposed; a contact hole
115
being filled with a conductor and extending through the interlayer insulating film
112
between an upper surface of the interlayer insulating film
112
and an upper surface of the source region
109
; and a source wiring
116
disposed on part of the upper surface of the interlayer insulating film
112
where the contact hole
115
is disposed.
The semiconductor device shown in
FIG. 19
is manufactured through various process steps. During these steps, a heavy metal impurity, such as iron, nickel or copper, attaches to the surface of a SOI layer
104
and gets inside the SOI layer
104
. For instance, a heavy metal impurity attaches to the surface of a SOI layer
104
through an etching process, and a heavy metal impurity gets inside the SOI layer
104
through an ion implantation.
Now consider the influence of these heavy metal impurities on a gate insulating film
106
. The heavy metal impurity attached to the surface of a SOI layer
104
can be removed by cleaning the surface of the SOI layer
104
with acid or alkali, before executing a thermal oxidation for forming the gate insulating film
106
. On the other hand, the heavy metal impurity present in a SOI layer
104
cannot be removed by cleaning. In a bulk substrate, a heavy metal impurity can be removed by forming a gettering site on its rear surface, whereas in a SOI substrate a gettering site cannot be formed on its rear surface by the presence of a buried oxide film
103
. As a result, the heavy metal impurity present in the SOI layer
104
is entrapped in the gate insulating film
106
, thus causing a reduction in the breakdown voltage and reliability of the gate insulating film
106
. As stated in the foregoing, the conventional semiconductor device using a SOI substrate has the problem that the heavy metal impurity present in a SOI layer cannot be removed by gettering.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a semiconductor device comprises: a SOI substrate of a stacked structure in which a semiconductor substrate, insulating layer, and semiconductor layer are stacked in this order; a transistor which is disposed in an element formation region of the SOI substrate and has a channel formation region selectively disposed in a main surface of the semiconductor layer, a gate insulating film on the channel formation region, a gate electrode on the gate insulating film, and source/drain regions disposed in the main surface of the semiconductor layer and adjacent the channel formation region; an interlayer insulating film on the transistor; a polycrystal semiconductor region selectively disposed such as to make no contact with the gate insulating film, on part of the main surface of the semiconductor layer where the source/drain regions are disposed; and a contact hole being filled with a polycrystal semiconductor and extending through the interlayer insulating film between an upper surface of the interlayer insulating film and an upper surface of the polycrystal semiconductor region.
According to a second aspect, a semiconductor device comprises: a SOI substrate of a stacked structure in which a semiconductor substrate, insulating layer, and semiconductor layer are stacked in this order; a transistor which is disposed in an element formation region of the SOI substrate and has a channel formation region selectively disposed in a main surface of the semiconductor layer, a gate insulating film on the channel formation region, a gate electrode on the gate insulating film, and source/drain regions disposed in the main surface of the semiconductor layer and adjacent the channel formation region; and a polycrystal semiconductor region selectively disposed such as to make no contact with the gate insulating film, on part of the main surface of the semiconductor layer where the source/drain regions are disposed.
According to a third aspect, the semiconductor device of the second aspect further comprises: an-interlayer insulating film on the transistor; and a contact hole being filled with a polycrystal semiconductor and extending through the interlayer insulating film between an upper surface of the interlayer insulating film and an upper surface of the polycrystal semiconductor region.
According to a fourth aspect, the semiconductor device according to any one of the first to third aspects further comprises an element isolation insulating film disposed in the main surface of the semiconductor layer in the element isolation region of the SOI substrate, wherein the polycrystal semiconductor region is disposed such as to make no contact with the element isolation insulating film.
According to a fifth aspect of the invention, a semiconductor device comprises: a SOI substrate of a stacked structure in which a semiconductor substrate, insulating layer, and semiconductor layer are stacked in this order; a transistor which is disposed in an element formation region of the SOI substrate and has a channel formation region selectively disposed in a main surface of the semiconductor layer, a gate insulating film on the channel formation region, a gate electrode on the gate insulating film, and source/drain regions disposed in the main surface of the semiconductor layer and adjacent the channel formation region; and a first polycrystal semiconductor region selectively extending through the insulating layer between an upper surface of the insulating lay
Yamaguchi Yasuo
Yamamoto Hidekazu
Doan Theresa T.
Wille Douglas
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