Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2001-07-11
2002-05-28
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S057000
Reexamination Certificate
active
06396310
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of Korean Application No. 2000-40990, filed Jul. 18, 2000, the disclosure of which is hereby incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention generally relates to integrated circuit devices, and more particularly, to current sense amplifiers.
Semiconductor memory devices may include a plurality of memory cells. Data may be stored in the memory cells and/or read from the memory cells. Typically, data stored in the memory cells is provided to a bit line sense amplifier via a bit line or a plurality of bit lines, so that the voltage level of the bit line or lines may be sensed and amplified. A word line may be enabled in response to a /RAS command. When a word line is enabled, data stored in all of the memory cells connected to the word line may be transmitted to bit lines corresponding to the respective memory cells. During transmission, the voltage levels of the bit lines may increase or decrease. Complementary bit lines correspond to adjacent memory cells. Complementary bit lines may maintain a voltage level that is pre-charged to an initial bit line voltage.
Accordingly, predetermined voltage differences may be generated between the bit lines and the complementary bit lines connected to bit line sense amplifiers. During operation of the bit line sense amplifiers, the voltage difference between the bit lines and the corresponding complementary bit lines may be amplified. Some of the output lines of the bit line sense amplifiers may be selected by a column selection circuit and connected to data input output lines. The column selection circuit may be activated in response to a /CAS active command. The time between a /RAS active command and a /CAS active command may be referred to as “tRCD”, i.e. a /RAS to /CAS delay time. The outputs of the bit line sense amplifiers transmitted to the data input output lines may also be sensed and amplified by data line sense amplifiers, for example, current sense amplifiers, and then output to a plurality of pads via a series of output buffers.
Now referring to
FIG. 1
, a block diagram illustrating part of the above-described semiconductor memory device will be described. Data of a bit line BL and a complementary bit line /BL may be coupled to a bit line sense amplifier
110
and may be transmitted to a pair of data input output lines DIO and /DIO, respectively, in response to a column selection signal CSL. The pair of data input output lines DIO and /DIO are connected to a current sense amplifier
150
via an input output MUX
140
. A data line sense amplifier, for example, current sense amplifier
150
, may sense and amplify the current of the data input output line pair DIO and /DIO and may determine a voltage level for the data input output line pair DIO and /DIO. The input output MUX
140
determines which memory block to connect the current sense amplifier
150
to when the current sense amplifier
150
is shared by at least two memory blocks.
Predetermined amounts of current i
1
and i
2
flow on the data input output line pair DIO and /DIO from a load transistor
130
, which may be, for example, a current source. For example, when the bit line sense amplifier
110
outputs a bit line BL at a logic high voltage level and a complementary bit line /BL at a logic low voltage level, a current that flows through a first load transistor
131
in response to a loading signal LOAD is typically smaller than a current that flows through a second load transistor
132
. This is due to the fact that the drain to source current Ids of the first load transistor
131
is smaller than the Ids of the second load transistor
132
as the drain to source voltage Vds of the first load transistor
131
is smaller than the Vds of the second load transistor
132
. Current flowing through the first load transistor
131
and current flowing through the second load transistor
132
may be applied to the data input output line DIO and the complementary data input output line /DIO, respectively.
Now referring to
FIG. 2
, a circuit diagram of the current sense amplifier of
FIG. 1
will be described. The current sense amplifier
150
may include sensing transistors
201
and
202
, load resistors
203
and
204
and a switching transistor
205
. The sensing transistors
201
and
202
may have similar electrical characteristics, and their sources are connected to the pair of data input output lines DIO and /DIO, respectively. The gate and drain of the sensing transistor
201
are cross-connected to the drain and gate of the sensing transistor
202
, respectively, as shown. The drains of the sensing transistors
201
and
202
are the outputs V
1
and V
2
of the current sense amplifier
150
. The load resistors
203
and
204
may be diode-type transistors, and may have similar electrical characteristics. For example, load resistors
203
and
204
may have the same resistance. The switching transistor
205
may provide a current path for flowing certain amounts of current supplied from the load transistors
131
and
132
of
FIG. 1
to a ground in response to the activation of a sensing enable signal PIOSE.
The switching transistor
205
may be turned on in response to the sensing enable signal PIOSE. Current i
1
flowing on the data input output line DIO is typically different from current i
2
flowing on the data input output line /DIO, due to the voltage difference between the bit line BL and the complementary bit line /BL caused by the operation of the bit line sense amplifier
110
as described in the example above. For example, when the current i
1
of the data input output line DIO is smaller than the current i
2
of the complementary data input output line /DIO, the first output voltage V
1
decreases, while the second output voltage V
2
increases. The first and second output voltage values V
1
and V
2
may be applied to the loading resistors
203
and
204
, respectively, and may become the results of sensing made by the current sense amplifier
150
. The first and second output voltage values V
1
and V
2
of the current sense amplifier
150
may then be transmitted to a latch-type sense amplifier and latched thereby (not shown).
The operation of the current sense amplifier
150
is typically stable once the voltage difference between the bit line BL and the complementary bit line /BL has been increased significantly by the bit line sense amplifier
110
during the time tRCD. In other words, the voltage difference between the bit line BL and the complementary bit line /BL at a time t
2
, shown in
FIG. 3
, is a stable voltage difference for the current sense amplifier
150
. If, on the other hand, the current sense amplifier
150
operates at a time t
1
, i.e., where the voltage difference between the bit line BL and the complementary bit line /BL is not sufficiently increased by the bit line sense amplifier
110
during the time tRCD, it may take a long time for the current sense amplifier
150
to sense and amplify the current difference between the data input output line pair DIO and /DIO. If the difference between the bit line BL and the complementary bit line /BL is not sufficiently increased during the time tRCD as discussed above, the difference between the first and second output voltage values V
1
and V
2
may be small enough to cause the latch-type sense amplifier to malfunction.
SUMMARY OF THE INVENTION
Integrated circuit memory devices according to some embodiments of the present invention include a current sense amplifier having first and second cross-coupled sensing transistors. In some embodiments of the present invention, the sensing transistors may be PMOS transistors. First and second data lines are electrically coupled to the source of the first sensing transistor and the source of the second sensing transistor, respectively. The current sense amplifier includes a first load transistor that has a source electrically connected to a drain of the first sensing transistor and a gate of the second sensing transistor and a second load transistor i
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Tran Toan
LandOfFree
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