Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-06-23
2002-06-11
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S643000, C438S651000, C438S653000
Reexamination Certificate
active
06403472
ABSTRACT:
BACKGROUND OF INVENTION
This invention relates to the insertion of resistors in integrated-circuit memory or logic, specifically as related to semiconductor contacts.
DISCUSSION OF PRIOR ART
Resistors of high value (starting at 1 k ohm) are often desired at many locations in a circuit. A typical application is the use of resistors in memory or logic to guard against single event upset phenomena in spacecraft and other applications. Typically such resistors are patterned from a high sheet resistance film. It would be advantageous to integrate a high value resistor into a semiconductor contact, thus avoiding the area penalty for using such resistors repetitively over the surface of the circuit.
Chen et al. (U.S. Pat. No. 5,665,629) explains the formation of a highly-resistive layer over contact openings using a CVD or physical deposition process, controlling the resistivity of the layer through control of the proportion of silicon in the deposition process, and subsequently performing a pattern mask and etch of the deposited material to remove selectively the deposited resistive layer.
Manning (U.S. Pat. Nos. 5,159,430 and 5,232,865) explains the formation of polysilicon-filled vias in contact with a silicon device and subsequently implanting oxygen or nitrogen to increase the resistance of the polysilicon plus. A high-temperature anneal at about 950 C. is carried out to stabilize the resistor value. Since load resistors are required only in some of the contacts, Manning's process involves fabricating the resistor contacts in a separate step, (i.e., two mask steps are required in order to fabricate all the contacts). An annealing temperature of 950° C. is high for very shallow doped devices, which can cause dopant spreading and affect junction widths. It is therefore preferable to form a high-value resistor using a lower-temperature process.
These prior-art methods explain the formation of a high-value resistor by either introducing silicon in an SiO
2
layer or introducing oxygen or nitrogen into an Si layer, (i.e., by forming off-stoichiometric structures).
OBJECTIVES, AND ADVANTAGES
The invention simplifies the prior art by converting desired silicon substrate material in a contact to a material with a desired higher resistivity, thereby eliminating the need to incorporate an added resistive layer.
REFERENCES:
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patent: 6051494 (2000-04-01), Iwamatsu et al.
patent: 6146934 (2000-11-01), Gardner et al.
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Wolf, “Silicon Processing for the VLSI Era—vol. 2 Process Integration”, Lattice Press, 1990, p. 128.*
Wolf, “Silicon Processing for the VLSI Era; vol. 2—Process Integration”, Lattice Press, 1990, p. 132.*
European Search Report.
Czagas Joseph A.
Woodbury Dustin A.
Brewster William M.
Dang Trung
Fogg Slifer Polglaze Leffert & Jay PA
Harris Corporation
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