Silver metallization by damascene method

Details Silver metallization by damascene method Silver metallization by damascene method

2000-05-02

2002-06-25

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S751000, C257S753000, C257S765000

Reexamination Certificate

active

06410985

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the formation of integrated circuit interconnect structures, and more specifically to a technique for forming silver metal interconnects within integrated circuit devices. The technique is particularly adapted for use with very small device geometries.
2. Description of the Prior Art
As device geometries within integrated circuits shrink, interconnect—conductive lines connecting devices to each other and to input and output pads—are becoming an obstacle to achieving greater device densities. In order to fit a larger number of devices on the same size die or on a smaller die, a larger number of interconnects must also be formed within a given area, and must continue to effectively conduct signals across relatively substantial distances on the die. Since interconnects typically run parallel to each other on a given metallization level, either the interconnect size (width or cross-sectional area) or the distance between adjacent interconnects, or both, must be reduced to increase the number of interconnects which may fit on a fixed-size die for carrying signals between devices. Reducing an interconnect's width or cross-sectional area increases the resistance of the interconnect, requiring larger voltages and/or currents to drive signals carried by the interconnects. Reducing the distance between adjacent interconnects creates a greater potential for capacitive coupling and signal errors.
One approach to increasing the number of interconnects which may be formed in a given area involves utilizing lower resistivity metals. Interconnects are typically formed of aluminum, which has a resistivity of about 2.7 &mgr;&OHgr;cm. By utilizing lower resistivity metals, such as copper (1.7-1.8 &mgr;&OHgr;-cm) or silver (1.2-1.5 &mgr;&OHgr;-cm), inter-connects with smaller widths and cross-sectional areas could be formed without increasing the total resistance of the interconnect. Thus, a larger number of inter-connects could be formed within a given area without impacting performance.
Unfortunately, some lower resistivity metals are incompatible with existing techniques for forming interconnects. A typical process for forming aluminum metal or aluminum alloy interconnects in accordance with the known art is depicted in
FIGS. 5A through 5D
. Current technology in metallization of integrated circuits involves forming an aluminum metal or alloy layer
502
over substrate
504
including devices and device contacts
506
formed through one or more dielectric layers
508
,
510
over the devices, as depicted in FIG.
5
A. In the embodiment depicted, dielectric
508
is a conformal dielectric layer such as an undoped oxide formed by chemical vapor deposition, while dielectric
510
is a spin-on glass. Contacts
506
may be formed of various materials such as tungsten or tungsten and polysilicon in the contact holes.
Aluminum layer
502
is then patterned by forming a photoresist layer over aluminum layer
502
and exposing and developing the photoresist to leave patterned resist lines
512
, as illustrated in FIG.
5
B. Aluminum layer
502
is then plasma etched with resist lines
512
in place to remove those portions of aluminum layer
502
which are not protected by resist lines
512
, leaving interconnects
514
as depicted in FIG.
5
C. Interconnects
514
are shown in cross-section in
FIG. 5C
, but may extend for substantial distances over the die to another contact or input/output pad (not shown). Photoresist lines
512
are then removed, and a dielectric layer
516
is deposited in the gaps between interconnects
514
and over interconnects
514
by plasma deposition and/or by spin-on dielectrics, as illustrated in FIG.
5
D. Additional levels of metallization and vias are added, if necessary, by repeating the steps depicted.
The methodology depicted above and the many variants known in the art suffer from the limitation that the metallization layer (aluminum
502
in the depicted example) must be etchable with the patterned photoresist in place. In effect, the metallization layer must be etchable at temperatures below approximately 200° C. Above that temperature, conventional polymer photoresists begin breaking down. Plasma or reactive ion etching may be utilized to etch aluminum below that temperature since aluminum reacts with halogens, such as chlorine or fluorine ions, to form a halide which is sufficiently volatile to be removed at low temperatures. Combined with ion bombardment, this reaction allows aluminum to be anisotropically etched to form interconnects with vertical sidewalls.
Metals having lower resistivities, such as copper or silver, do not form sufficiently volatile compounds at temperatures low enough to prevent photoresists from breaking down. Alternative etch processes, such as wet etching, generally produce unsatisfactory results, such as undercutting. Alternative masking processes to etching the conductive material with a photoresist mask, such as “hard” masking with deposited oxide layers, introduce an unreasonable level of additional complexity into the overall process. Thus, conventional processing techniques of the type described above may not be adapted in a satisfactory manner to produce interconnects with lower resistivity metals, particularly with silver. Efforts are currently being directed to developing processes for forming interconnects with copper, since silver is more expensive and less malleable than copper. Additionally, problems with silver migration in the presence of moisture are known in the art, making the use of silver unreliable.
It would be desirable to provide a processing method, and a resulting structure, which would permit the use of low resistivity metal interconnects in an integrated circuit. It would further be desirable for a method producing such low resistivity metal interconnects to be compatible with presently available processing techniques, and to be available without significantly adding to processing complexity.
SUMMARY OF THE INVENTION
Silver interconnects are formed by etching deep grooves into an insulating layer over the contact regions, exposing portions of the contact regions and defining the interconnects. The grooves are preferably etched with a truncated V- or U-shape, wider at the top than at any other vertical location, and have a minimum width of 0.25 &mgr;m or less. An optional adhesion layer and a barrier layer are sputtered onto surfaces of the groove, including the sidewalls, followed by sputter deposition of a seed layer. Where aluminum is employed as the seed layer, a zincating process may then be employed to promote adhesion of silver to the seed layer. The groove is then filled with silver by plating in a silver solution, or with silver and copper by plating in a copper solution followed by plating in a silver solution. The filled groove which results does not exhibit voids ordinarily resulting from sputter deposition of metal into such narrow, deep grooves, although seams may be intermittently present in portions of the filled groove where metal plated from the opposing sidewalls did not fuse flawlessly at the point of convergence. Portions of the silver and other layers above the insulating material are then removed by chemical-mechanical polishing, leaving a silver interconnect connected to the exposed portion of the contact region and extending over adjacent insulating regions to another contact region or a bond pad. Silver interconnects thus formed may have smaller cross-sections, and thus a greater density in a given area, than conventional metallic interconnects.


REFERENCES:
patent: 3686698 (1972-08-01), Akeyama et al.
patent: 3808470 (1974-04-01), Kniepkamp
patent: 5627102 (1997-05-01), Shinriki et al.
patent: 5645628 (1997-07-01), Endo et al.
patent: 5705230 (1998-01-01), Matanabe et al.
patent: 5723028 (1998-03-01), Poris
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5763953 (1998-06-01), Iijima et al.

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