Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-03-05
2002-08-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S166000, C438S907000
Reexamination Certificate
active
06429059
ABSTRACT:
The present invention relates to a semiconductor device that comprises thin semiconductor films having a crystalline structure, and to a method for producing it. In particular, it relates to the constitution of thin film transistors (hereinafter referred to as TFT) having an inverse stagger structure. It also relates to the constitution of semiconductor circuits, electro-optical devices and electronic instruments having those TFT.
The terminology “semiconductor device” referred to herein is directed to any and every device that functions on the basis of semiconductor characteristics; and TFT, semiconductor circuits, electro-optical devices and electronic instruments referred to herein is all within the category of that terminology, semiconductor device.
BACKGROUND OF THE INVENTION
TFT have heretofore been being used as switching elements in active matrix-type liquid crystal devices (hereinafter referred to as AMLCD). At present, devices with TFT circuits that comprise active layers of amorphous silicon films have a high market share. In particular, inverse stagger structures capable of being produced in simple processes are much employed for constructing TFT.
With recent developments in high-quality AMLCD, however, TFT are being required to have much better operating characteristics (especially for high operating speed). In such situations, amorphous silicon TFT are often unsatisfactory as their operating speed is not high, and high-quality devices comprising amorphous silicon films are difficult to produce.
Accordingly, polysilicon TFT have become much highlighted in place of amorphous silicon TFT, and TFT comprising polysilicon films as the active layers are being actively studied and developed in the art. At present, some polysilicon TFT devices are on the market.
Many reports have already been disclosed, relating to inverse stagger-type TFT structures comprising active layers of polysilicon films. For example, referred to is a report of “Fabrication of Low-Temperature Bottom-Gate Poly-Si TFTs on Large-Area Substrate by Linear-Beam Excimer Laser Crystallization and Ion Doping Method: H. Hayashi, et al., IEDM 95, pp. 829-832, 1995”.
In that report, they illustrated one typical example (
FIG. 4
) of inverse stagger structures comprising polysilicon films. However, inverse stagger structures of that type (that is, so-called channel-stop-type ones) have various problems.
First, in those structures, the active layers having an overall thickness of 50 nm or so are extremely thin. Therefore, in those, impact ionization at the junction of the channel-forming region and the drain region is occurred, whereby the structures are significantly deteriorated due to hot carrier implantation. For these reasons, a large LDD region (light doped drain region) must be formed in those structures.
In this connection, the most critical problem is how to control the LDD region. The LDD region requires extremely delicate control of the impurity concentration therein and the length of itself. In particular, the length control of the region is problematic. At present, the length of the LDD region is defined by mask patterning. In fine TFT, however, any minor patterning error in masking the LDD region will produce significant differences in TFT characteristics.
Another serious problem is that the sheet resistivity in the LDD region significantly varies depending on the variation in the thickness of the active layers. Moreover, the variation in the taper angle of the gate electrodes often causes the variation in the function of the LDD region.
In addition, the LDD region requires patterning, which directly complicates the production process while lowering the throughput. It is presumed that the production of the inverse stagger structure described in the report noted above requires at least 6 masks (up to the step of forming the source/drain electrodes).
As mentioned above, the channel-stop-type inverse stagger structure indispensably requires the transverse in-plane LDD region to be formed at the both sides of the channel-forming region, in which, however, a reproducible LDD region is extremely difficult to form.
SUMMARY OF THE INVENTION
The subject matter of the present invention is to provide a technique for producing highly-reliable and highly-reproducible semiconductor devices in an extremely simple process applicable to mass-production.
One aspect of the invention is a semiconductor device having a semiconductor film comprising a source region, a drain region and a channel-forming region, the semiconductor films having a crystalline structure,
wherein the source region and the drain region each have a laminate structure comprising at least a first conductive layer, a second conductive layer of which the resistance is higher than that of the first conductive layer, and a third semiconductor layer of which the conductivity type is the same as that of the channel-forming region, the layers being laminated in that order toward the gate-insulating film.
In one embodiment of the constitution of this aspect, the semiconductor film having a crystalline structure have a grain boundary distribution peculiar to fusion-crystallized films.
In another embodiment, the concentration profile of the impurity constituting the first and second conductive layers varies continuously from the first conductive layer to the second conductive layer.
In still another embodiment, the second conductive layer contains an impurity that varies continuously within the range of from 5×1017 to 1×1019 atoms/cm3.
In still another embodiment, two offset regions each having a different thickness exist between the channel-forming region and the second conductive layer.
In still another embodiment, an offset region of which the thickness is larger than that of the channel-forming region exists between the channel-forming region and the second conductive layer.
Another aspect of the invention is a semiconductor device having a gate electrode formed on a substrate having an insulating surface; a semiconductor film comprising a source region, a drain region and a channel-forming region, the semiconductor having a crystalline structure; and a source electrode and a drain electrode as formed on the source region and the drain region, respectively,
wherein the source region and the drain region each have a laminate structure comprising at least a first conductive layer, a second conductive layer of which the resistance is higher than that of the first conductive layer, and a third semiconductor layer of which the conductivity type is the same as that of the channel-forming region, the layers being laminated in that order toward the gate-insulating film, and
the source electrode and/or the drain electrode overlap(s) with the gate electrode on the channel-forming region.
Still another aspect of the invention is a semiconductor device having a semiconductor film comprising a source region, a drain region and a channel-forming region, the semiconductor film having a crystalline structure,
wherein the source region and the drain region each have a laminate structure comprising at least a first conductive layer, a second conductive layer of which the resistance is higher than that of the first conductive layer, and a third semiconductor layer of which the conductivity type is the same as that of the channel-forming region, the layers being laminated in that order toward the gate-insulating film, and
wherein an HRD structure comprising two offset regions each having a different thickness and the second conductive layer is formed between the channel-forming region and the first conductive layer.
In one embodiment of the constitution of this aspect, one of the two offset regions each having a different thickness is for offset in the in-plane direction and is formed of a semiconductor layer of which both the conductivity type and the thickness are the same as those of the channel-forming region, while the other is for offset in the thickness direction and is formed of a semiconductor layer of which the conductivity type is the same as that
Fukunaga Takeshi
Koyama Jun
Yamazaki Shunpei
Costellia Jeffrey L.
Niebling John F.
Nixon & Peabody LLP
Semiconductor Energy Laboratory Co,. Ltd.
Whitmore Stacy
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