Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
2001-09-05
2002-09-10
Cuchlinski, Jr., William A. (Department: 3661)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S099000, C700S100000, C700S101000, C700S102000, C700S103000, C700S121000, C700S213000, C414S936000, C414S937000, C414S938000, C414S939000, C414S940000, C414S941000, C204S290150, C204S298330
Reexamination Certificate
active
06449520
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates generally to an apparatus, method and medium for increasing the throughput of a semiconductor wafer processing facility. More particularly, the invention provides various efficiency enhancements for such a facility, including a multi-slot cool down chamber, the use of multiple wafer priority levels to control wafer movement, and a look-ahead scheduling process.
2. Related Information
Automated semiconductor fabrication facilities which employ a single-wafer, multi-chamber design are well known. As one example, the Centura model 5200 sold by Applied Materials, Inc. of Santa Clara, Calif. (see
FIG. 1
) provides a plurality of chambers arranged around a central processing station which includes a robot arm
101
for moving a silicon wafer
102
between the chambers. Each wafer is stepped through a series of processes (typically one per chamber) which results in the formation of various layers on the wafer which are later used to form a semiconductor device.
As shown in
FIG. 1
, two load lock chambers
109
and
110
may each include a cassette which forms a plurality of slots (
109
a
and
110
a
, respectively) for holding a number of wafers. As one example, each cassette may hold 25 wafers. A plurality of processing chambers
104
through
107
each include equipment which performs a processing step on a wafer inserted into the chamber through a corresponding slot (
104
a
through
107
a
). For example, one process chamber may perform a chemical vapor deposition (CVD) process on a wafer, while another chamber may perform an etching process. A process controller
111
, which may comprise a digital computer (such as an embedded Motorola 68040 CPU with a realtime operating system) including sequencing software, may be used to control the timing and movement of wafers through the various chambers to effect the desired process steps on each wafer.
In addition to the process chambers, an orientation chamber
103
may be included to orient each wafer prior to processing. This generally entails finding the center of a wafer inserted into the chamber and passing this center point information to process controller
111
so that robot arm
101
can properly orient the wafer prior to insertion into one of the process chambers. Additionally, a cool down chamber
108
is generally used to allow wafers to cool down between processing steps or after processing is completed.
In general, process controller
111
causes robot arm
101
to remove wafers from a load lock chamber
110
, orient the wafer in chamber
103
, move the wafer through one or more of the process chambers
104
through
107
according to a timed “recipe” for the wafer, cool down the wafer in cool down chamber
108
, and place the processed wafer into a load lock chamber
109
. Depending on the particular “recipe”, a wafer may be moved from load lock
110
to process C (chamber
107
), then to process A (chamber
106
), then cooled down (chamber
108
), then moved back to process C again (chamber
107
), cooled down again (chamber
108
), then moved to load lock
109
. Of course, more than one wafer may be processed simultaneously if the steps are properly synchronized.
Each wafer which is dispensed from load lock
110
may be stepped through the same process steps to produce the same type of wafer. Alternatively, different wafers from the same load lock may be programmed to undergo a different “recipe” involving different steps and/or process times, such that different types of wafers are produced.
A bottleneck has been found to occur in the conventional wafer processing method described above when multiple wafers are simultaneously processed in an overlapping sequence. This bottleneck has been found to occur at the cool-down chamber
108
. This cool-down chamber is needed primarily to prevent damage to load lock chamber
109
after heating a wafer in one of the processing chambers
104
through
107
, and also to cool down wafers between certain processing steps. However, the wafer processing steps are relatively short compared with the time required in cool down chamber
108
, thus causing the cool down chamber to limit the throughput of the entire apparatus. The fact that the conventional cool down chamber only has a single slot for holding a wafer also contributes to this bottleneck.
In addition to the bottleneck caused by the cool down chamber, conventional wafer scheduling techniques generally contemplate moving wafers sequentially based on their wafer identification number (i.e., the first wafer to be removed from load lock
110
will be deemed wafer #1, the second one will be deemed wafer #2, etc.) rather than on the status of the wafer process itself. The present inventors have found that this scheduling paradigm also results in a loss of efficiency.
For example, if wafer #1 is in process B (chamber
105
) and is ready to be moved to cool down chamber
108
, while at the same time wafer #2 is in load lock
110
and ready to be moved into process D (chamber
104
), the conventional scheduler will first move wafer #1 to the cool down chamber. However, for reasons which will become evident shortly, this may not be as efficient as first moving wafer #2 into process D (chamber
104
) prior to moving wafer #1 to the cool down chamber. Thus, potential efficiency is lost.
The above-described inefficiency is presented by way of simplified illustration in FIG.
2
. In
FIG. 2
, time periods are indicated on the horizontal axis and each potential processing step is shown on the vertical axis. Each numbered circle represents a single wafer, and arrows between circles represent wafer movement between chambers by way of a robot arm.
Suppose, for example, that a first wafer (wafer #1) is to be subjected to process A for one time period, process B for three time periods, then a cool down period before being moved out of the processing sequence. The aforementioned sequence constitutes the “recipe” for this wafer.
Assume that a second wafer (wafer #2) is to be subjected to process A for three time periods, process C for four time periods, then a cool down period. Other wafers #3 and #4, after being removed from a load lock cassette, will be subjected to similar processing sequences.
As can be seen at time period
0
in
FIG. 2
, the robot arm first moves wafer #1 into the chamber which performs process A (step
200
). Next, after a single time period, the robot arm moves wafer #1 from process A to process B (step
201
). Thereafter, wafer #2 is removed from the load lock area and moved into process A (step
202
) where it remains for three time periods.
At time period
4
, wafer #1 is ready to be moved to the cool down chamber, which occurs in step
204
. Thereafter, in step
205
, wafer #2 is moved to process C, where it remains for four time periods. Then, at time period
7
, wafer #1 is ready to be moved out of the cool down chamber, and this step occurs as indicated at
207
. However, it would have been more efficient at time period
7
to bring another new wafer into one of the processing chambers prior to removing cooled wafer #1 (i.e., there is no inefficiency in delaying the removal of a cooled wafer). As can be seen in step
208
, wafer #3 is not brought into process A until time period
8
because of the movement of cooled wafer #1 in step
207
. This inefficiency causes a decrease in wafer throughput.
Continuing with the scenario of
FIG. 2
, at step
209
wafer #2 is moved from process C to the cool down chamber. However, at the same time, wafer #4 could have been brought into process B, since that chamber was available and ready for use. Thus, step
210
(movement of wafer #4 into process B) was unnecessarily delayed for at least one time period. This sequence (moving a processed wafer before an unprocessed or “virgin” wafer) illustrates another inefficiency of conventional wafer processes.
Various manifestations of the aforementioned problem are illustrated mo
Lin Zhihong J.
Wang Chongyang
Applied Materials Inc.
Cuchlinski Jr. William A.
Hale & Dorr, LLP.
Marc McDieunel
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