Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-05-28
2002-06-11
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S642000, C438S653000
Reexamination Certificate
active
06403462
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a method of manufacturing semiconductor devices.
As recent semiconductor devices increase in circuit density and performance, interconnections are getting finer and making more use of multilevel structures. Aluminum, Al, has been used as a material for interconnection because it is easy to work and has a relatively low resistance.
The finer interconnections and multilevel structures have given rise to an interconnection problem. Specifically, as interconnections become finer, the cross-sectional area of the interconnection becomes increasingly small. Since no measure has been taken to reduce the signal current, the current density has been increasing, permitting electromigration (EM) to give rise to broken wires or short circuits, which becomes a serious problem.
To solve the problem, a method has been proposed. In the method, diffusion barrier layers against Al are formed in the Al interconnections and the Al interconnections are divided into fine interconnections shorter than the Blech critical length.
The method is based on the fact that when an interconnection is shorter than a specific length, or the Blech critical length, the diffusion of atoms due to the stress gradient in the interconnection is balanced against the diffusion of atoms by current wind, preventing Al atoms from drifting by EM (refer to I. A. Blech, E. Kinsborn, “Thin Solid Films,” 25, 337, 1975).
In the method, a Cu film is deposited on an Al interconnection embedded in an interconnection groove. Next, Cu or AlCu compound in the Cu film is diffused throughout the Al interconnection by a heat treatment. Then, Cu is allowed to precipitate in the Al crystal grain boundary, which causes diffusion barrier layers to divide the Al interconnection into fine Al interconnections shorter than the Blech critical length.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device manufacturing method which enables the formation of highly electromigration-resistant and stress-migration-resistant interconnection divided into fine interconnections shorter than the Blech critical length without increasing the interconnection resistance.
The foregoing object is accomplished by providing a semiconductor device manufacturing method having the steps of: forming an interlayer insulating film on a semiconductor substrate; making a connection hole in the interlayer insulating film; filling an inside of the connection hole with a conductive film which is made of a first substance, is thicker than the depth of the connection hole, and has a crystal grain boundaries; forming on the conductive film a diffusion source film which is made of a second substance and to be a diffusion barrier layer against the first substance; forming a diffusion barrier layer in the connection hole against the first substance in the crystal grain boundary by causing the second substance to selectively diffuse into the crystal grain boundary at the same time or after the time of formation of the conductive film so as to the diffusion barrier layer to divide the conductive film into regions shorter than the Blech critical length; and removing the conductive film and the diffusion source film outside the connection hole to form an interconnection composed of the conductive film in the connection hole.
With the present invention, the inside of the connection holes are filled with the conductive film made of the first substance acting as interconnections thicker than the depth of the connection holes. This prevents the second substance from precipitating in the crystal grain in the conductive film in the connection holes even when the second substance has precipitated at high concentration in the crystal grain in the conductive film outside the connection holes in diffusing the second substance (material for the diffusion barrier layer). On the other hand, the diffusion barrier layer can be formed as far as the bottom of the connection holes, making use of the fact that the diffusion of the second substance in the crystal grain boundary (grain boundary diffusion) is faster than the diffusion in the crystal grain (volume diffusion).
Specifically, for the conductive film in the connection holes, the second substance is allowed to selectively precipitate in the crystal grain boundary, which prevents the second substance from precipitating in the crystal grain. The precipitation of the second substance in the crystal grain contributes to an increase in the interconnection resistance. Consequently, with the present invention, it is possible to form highly electromigration-resistant fine interconnections without increasing the interconnection resistance.
On the other hand, stress-migration due to the difference in thermal expansion coefficient between the interconnection and the interlayer insulating film is such a faulty interconnection as a broken interconnection caused by the diffusion of vacancies into a void earlier formed and the accumulation of vacancies in the void.
Such a faulty interconnection can be prevented by suppressing the long-distance diffusion of voids. In the present invention, the second substance is caused to diffuse into the crystal grain boundary and diffusion barrier layers made of the second substance are allowed to divide the interconnection into fine interconnections. Because the diffusion barrier layers suppress the long-distance diffusion of voids, stress-migration can be prevented. As explained earlier, the formation of such diffusion barrier layers leads to no increase in the interconnection resistance. Therefore with the present invention, the stress-migration resistance of interconnections can be also increased, without increasing the interconnection resistance.
Another object of the present invention is to provide a semiconductor device capable of increasing the electromigration of interconnection, regardless of the interconnection structure (a damascene structure or an RIE structure).
The foregoing object is accomplished by providing a semiconductor device having a semiconductor substrate in which an element is formed; and an interconnection formed on the semiconductor substrate and connected to the element, wherein the interconnection is formed of fine interconnections divided by diffusion barrier layers so as to be shorter than the Blech critical length, the diffusion barrier layers are made of a material including a main component element of the fine interconnections which acts as a diffusion barrier against the main component element of the fine interconnections, and an expression is fulfilled: (D
B
/D
line
)/L
W
≦0.1, where D
B
is a mutual diffusion coefficient of the main component element in the diffusion barrier layers, D
line
is a self diffusion coefficient of the main component element and L
W
[&mgr;m] is an average layer thickness of the diffusion barrier layers in the longitudinal direction of the interconnection.
The inventors' research has shown that if the above conditions are fulfilled, the electromigration resistance of interconnections can be increased, regardless of the interconnection structure, as described in detail in the embodiments below. Therefore with the present invention, the electromigration resistance of interconnections can be increased, regardless of the interconnection structure. And the diffusion barrier layer also suppress the long-distance diffusion of voids, high stress-migration-resistant can be achieved.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
REFERENCES:
patent: 4057824 (1977-11-01), Woods
patent: 4529621 (1985-07-01), Ballard
patent: 4989064 (1991-01-01), Kubokoya et al.
patent: 5382831 (1995-01-01), Atakov et al.
patent: 5428233 (1995-06-01), Walczyck
Hasunuma Masahiko
Ito Sachiyo
Kaneko Hisashi
Shima Shohei
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Peralta Ginette
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