Method for forming semiconductor device

Details Method for forming semiconductor device Method for forming semiconductor device

2000-06-01

2002-08-27

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S619000

Reexamination Certificate

active

06440846

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for forming a semiconductor device, and more particularly, the present invention relates to the method for forming the semiconductor device using a photo-curing resin.
This application is a counterpart of Japanese application Serial Number 289102/1999, filed Oct. 12, 1999, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
In general, a method for burying a via-hole is the following:
FIG.
3
A-
FIG. 3I
are cross-sectional views showing a method for forming GaAs IC (Integrated Circuit).
As shown in
FIG. 3A
, a GaAs substrate
1
is provided.
As shown in
FIG. 3B
, a first photo-resist
2
is coated on the GaAs substrate
1
. A plurality of first photo-resist patterns
2
are formed on the GaAs substrate
1
using photo-lithography technique. As a result, a plurality of openings
3
are formed between the first photo-resist patterns
2
, respectively. The first photo-resist patterns
2
serve as first masks.
As shown in
FIG. 3C
, a plurality of via-holes
4
having a depth of 70 &mgr;m are formed in the GaAs substrate
1
using dry etching technique.
As shown in
FIG. 3D
, after removing the first photo-resist patterns
2
, a plurality of second photo-resist patterns
5
is formed on the GaAs substrate
1
using photo-lithography technique. In this time, a plurality of openings
6
are formed so as to expose the openings
3
. The second photo-resist patterns
5
serve as second masks.
As shown in
FIG. 3E
, a plurality of plating gold (Au)
7
is formed in the via-holes
4
using electroless plating technique with the second masks. Then, the second masks is removed.
As shown in
FIG. 3F
, a polyimide
8
having a coefficient of viscosity of 35 cp is formed so as to extend from the GaAs substrate
1
to the plating gold
7
. Here, a polyimide coating condition: the number of rotations is 1000 [rpm], a thickness on the GaAs substrate
1
is 10 &mgr;m. Then, an entire structure is baked at one hour, 350° C. As a result, the polyimide
8
is cured. Adhesion between the plating gold
7
and the polyimide
8
is improved and hardness for the polyimide
8
is increased. As a result, the cured polyimide
8
can improve to resist to impact when polishing as reinforcing material.
As shown in
FIG. 3G
, the cured polyimide
8
is etched back. As a result, the cured polyimide
8
is buried in the via-holes
4
As shown in
FIG. 3H
, the entire structure put up a supporting base of a glass substrate
10
via a wax at the via-holes forming side. Then, the GaAs substrate
1
and the plating gold
7
are polished a thickness of 50 &mgr;m from a back side until exposing the polyimide
8
.
As shown in
FIG. 3I
, a backside electrode
12
, for example gold (Au), is formed on the polished surface
11
using vacuum evaporation technique. The backside electrode
12
is electrically connected to the plating gold
7
.
It is desired to improve reliability of bonding and simplify process flow without decreasing electrical characteristics.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for forming a semiconductor device that can improve reliability of bonding and simplify process flow without decreasing electrical characteristics.
According to one aspect of the present invention, for achieving the above object, there is provided a method for forming a semiconductor device comprising: providing a substrate having a first main surface and a second main surface opposite to the first main surface; forming a via-hole in the first main surface of the substrate; forming a plated layer in the via-hole; burying a photo-resin on the plated layer in the via-hole; curing the photo-resin; removing the substrate and the plated layer from the second main surface side until exposing the cured photo-resin; removing the cured photo-resin; and forming an electrode layer on the removed surface so as to electrically connect to the plated layer.


REFERENCES:
patent: 5037780 (1991-08-01), Fujimoto et al.
patent: 5191479 (1993-03-01), Tsuchida
patent: 5316610 (1994-05-01), Tamaki et al.

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