Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-12-05
2002-08-06
Talbott, David L. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S107000, C438S108000, C438S110000, C438S121000, C438S122000, C438S124000, C438S125000, C438S126000, C438S127000
Reexamination Certificate
active
06429048
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to packaging for integrated circuit (IC) devices, and in particular to a method of fabricating a metal foil laminated package for ball grid arrays.
BACKGROUND OF THE INVENTION
As thermal and electrical requirements of IC packages become more demanding, advanced forms of package construction have been developed. In general, array packaging such as Pin-Ball Grid Array (PBGA) provides for a high density of interconnects relative to the surface area of the package. However, typical PBGA packages are characterized by a convoluted signal path, giving rise to high impedances and an inefficient thermal path which results in low thermal dissipation performance.
Applicants' prior Tape Ball Grid Array (TBGA) product is an advanced IC package having straight signal paths and a copper backed, die down construction which enjoys enhanced performance over prior art PBGA packages. However, this TBGA design suffers from complex construction in which heatsinks are precisely laminated to the substrate with expensive polyimide tape in a post etch operation. Further, the presence of polyimide between the heatsink and the copper traces of the tape minimizes the effectiveness of routing the traces in close proximity to the grounded heatsink.
Additional prior art packages include the well known Super BGA package which has an organic substrate attached to a metal backing. However, the organic layer between the I/O balls and the thermal grounding of the heatsink results in severe limitations to the conduction of heat flowing to the balls from the metal backing.
Similarly, the prior art Prolinx™ BGA and STI™ BGA are built up structures over metal backings wherein the built up layered structures include silver filled epoxy to act as a layer-to-layer interconnect. However, they require machined cavities and complex routing techniques which reduce cost effectiveness. From a cost point of view, these products are considered to be expensive, and require very specialized construction techniques to fabricate them.
Further examples of prior art Tab Grid Arrays are described in:
U.S. Pat. No. 5,397,921 issued Mar. 14, 1995;
U.S. Pat. No. 5,409,865 issued Apr. 25, 1995;
U.S. Pat. No. 5,843,808 issued Dec. 1, 1998.
SUMMARY OF THE INVENTION
According to one aspect of the present invention there is provided an IC package having a laminate substrate design built using copper sheet instead of the glass reinforced resin normally used. The metal foil laminated package of the present invention eliminates the requirement for expensive polyimide tape. A further advantage of the IC package of the present invention is that the accuracy of the artwork relative to the die attach cavity is an inherent feature of the way the package is manufactured. This precludes any alignment inaccuracies of tape to heatsink attachment which can cause problems in prior art. According to a further aspect of the invention, multiple trace layers are provided for interconnection between levels by means of laser drilled vias and a post plating interconnect. These features offer enhanced routing density and electrical performance when compared to single layer designs.
In one embodiment, some of the external I/O balls of the package are short circuited to the heatsink to act as a close loop ground. The ground path is short circuited via wire bond to the ground trace on the routed metal of the interconnect structure of the package and also to the ground pads of the IC device.
REFERENCES:
patent: 5397921 (1995-03-01), Karnezos
patent: 5409865 (1995-04-01), Karnezos
patent: 5572405 (1996-11-01), Wilson et al.
patent: 5759737 (1998-06-01), Feilchenfeld et al.
patent: 5843808 (1998-12-01), Karnezos
patent: 6207354 (2001-03-01), Bhatt et al.
Fan Chun Ho
Lau Pik Ling
McLellan Neil
Tsang Kwok Cheung
ASAT Ltd.
Keating & Bennett LLP
Talbott David L.
Zarneke David A.
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