Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-07-21
2002-08-27
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S315000, C438S266000
Reexamination Certificate
active
06441429
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to formation of memory devices and more particularly to a method of forming a split-gate EPROM, flash memory device having a floating gate electrode with a sharp polysilicon peak.
2. Description of Related Art
U.S. Pat. No. 5,445,999 of Thakur et al. for “Advanced Technique to Improve the Bonding Arrangement on Silicon Surfaces to Promote Uniform Nitridation” describes formation of a native oxide layer on a substrate with silicon molecular clusters. Radiant energy is used in the presence of a reactive gas to convert silicon molecular clusters and already dangling bonds into a uniform dangling bond configuration on a silicon or polysilicon substrate.
U.S. Pat. No. 5,492,854 of Ando for “A Method of Forming a Semiconductor Device” describes a process including forming a capacitor with a lower electrode composed of polysilicon. The device is heated in an atmosphere containing a SiH
4
gas to remove a native oxide film on a surface of the lower electrode. Then a silicon nitride film is formed in an atmosphere excluding oxygen.
U.S. Pat. No. 5,614,747 of Ahn et al. for “Method for Manufacturing a Flash EEPROM Cell” describes forming a floating gate structure.
SUMMARY OF THE INVENTION
An object of this invention is to improve the erase speed of a split-gate EPROM, flash memory device.
Another object of this invention is to shrink the cell dimensions of a split-gate EPROM, flash memory device.
A method in accordance with this invention forms split gate electrode MOS FET devices. The method involves forming split gate electrode MOS FET devices including the following steps. Form a tunnel oxide layer over a semiconductor substrate; form a first doped polysilicon layer over the tunnel oxide layer followed by development of a native oxide layer upon the surface of the first doped polysilicon layer, the first doped polysilicon layer having an upper surface. Then, form a silicon nitride layer over the first doped polysilicon layer. Form a photoresist mask with a floating gate pattern to provide a cell defining mask over the silicon nitride layer. Etch through the photoresist mask to pattern the silicon nitride layer into the pattern of the floating gate. Remove the photoresist. Etch to remove the native oxide layer from the surface of the exposed first doped polysilicon layer. Form a polysilicon oxide (polyoxide) masking cap over the upper surface of the first doped polysilicon layer with the masking cap having narrow encroachment wings on its lateral portions. Pattern a gate electrode stack formed by the tunnel oxide layer and the first doped polysilicon layer in the pattern of the masking cap with a sharp bird's beak peak on the periphery of the upper surface of the first doped polysilicon layer. Form inter-polysilicon dielectric and control gate layers over the substrate covering the stack; and pattern the inter-polysilicon dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Preferably, form FOX regions and then form active regions in the substrate prior to forming the tunnel oxide layer; form a silicon nitride floating gate mask over the first doped polysilicon layer; etch the tunnel oxide layer and the first doped polysilicon layer using the cap as a mask to form the floating gate electrode; and the bird's beak has a width from about 1,500 Å to about 2,000 Å a distance of 1,200 Å below the peak, and the angle of the wall of the floating gate proximate to the peak where the floating gate faces the polyoxide cap is from about 40° to about 50°.
Alternatively, the native oxide layer is removed from the first doped polysilicon layer by an etching process prior to forming the silicon nitride layer over the first doped polysilicon layer, and the bird's beak has a width of about 700 Å at a distance of 1,200 Å below the peak, and the angle of the wall of the floating gate proximate to the peak where the floating gate faces the polyoxide cap is from about 5° to about 15°.
In accordance with this invention, a split gate electrode MOS FET device includes a tunnel oxide layer over a semiconductor substrate; a floating gate electrode layer over the tunnel oxide layer; a cap over the first doped polysilicon layer; and a floating gate electrode stack formed from the tunnel oxide layer and the first doped polysilicon layer in the pattern of the cap with the first doped polysilicon layer comprising a floating gate electrode with a cross-sectional bird's beak having a sharp peak along the periphery thereof adjacent to the cap. Form inter-polysilicon dielectric and control gate layers over the substrate covering the stack. The inter-polysilicon dielectric and control gate layers comprise adjacent mirror image split gate electrode pairs. Preferably, the floating gate electrode comprises a first doped polysilicon layer; the cap on the surface of the first doped polysilicon layer forms a polysilicon oxide cap on the surface of the first doped polysilicon layer; the tunnel oxide layer and the first doped polysilicon layer are patterned in the shape of the cap forming the floating gate electrode; the bird's beak has a width from about 1,500 Å to about 2,000 Å a distance of 4,000 Å below the peak; and the angle of the wall of the floating gate proximate to the peak where the floating gate faces the polyoxide cap is from about 40° to about 50°.
Alternatively, the native oxide layer is removed from the first doped polysilicon layer by an etching process prior to forming the silicon nitride layer over the first doped polysilicon layer, and the bird's beak has a width of about 700 Å at a distance of 1,200 Å below the peak, and the angle of the wall of the floating gate proximate to the peak where the floating gate faces the polyoxide cap is from about 5° to about 15°.
Subsequently, source regions are formed self-aligned with the gate electrode stack by ion implantation while the future drain region sites are covered with a mask. Then sidewall spacers are formed and the source/drain regions are doped with a greater dopant level resulting in the source regions as compared with the drain regions.
In this embodiment of the invention the native oxide is removed before forming the silicon nitride over the first doped polysilicon layer.
REFERENCES:
patent: 5045488 (1991-09-01), Yeh
patent: 5445999 (1995-08-01), Thakur et al.
patent: 5492854 (1996-02-01), Ando
patent: 5493138 (1996-02-01), Koh
patent: 5614747 (1997-03-01), Ahn et al.
patent: 5811853 (1998-09-01), Wang
patent: 5907172 (1999-05-01), Sheu
patent: 6130132 (2000-10-01), Hsieh et al.
patent: 6200859 (2001-03-01), Huang et al.
patent: 6225163 (2001-05-01), Bergemont
patent: 6307770 (2001-10-01), Oya
Hsieh Chia-Ta
Kuo Di-Son
Lin Yai-Fen
Sung Hung-Cheng
Elms Richard
Jones Graham S.
Taiwan Semiconductor Manufacturing Company
Wilson Christian D.
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