Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-12-18
2002-04-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S623000
Reexamination Certificate
active
06380076
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to the dielectric filling of electrical wiring planes in an integrated circuit.
Integrated circuits consist of a multiplicity of individual patterns which are in most cases arranged in layers on a substrate. Electronic components such as resistors, capacitors, diodes, transistors etc. are usually manufactured in one substrate. The individual components are then electrically interconnected in one or more wiring planes (so-called metalization planes) located thereabove.
A process which is used for the electrical wiring provides for the deposition of a conductive layer on a substrate. The conductive layer is then photolithographically patterned so that conductor tracks with an intermediate trench are produced. The trench is usually filled with a dielectric of silicon oxide. For this purpose, for example, doped silicon oxides such as borosilicate glass, phosphorosilicate glass or arsenosilicate glass or mixtures of these materials are used. The doped silicate glasses have the property of becoming fluid at high temperatures. This makes it possible to fill the trench with an insulating dielectric.
However, the doped silicate glasses have the disadvantage that they exhibit a high dielectric constant of approx. 4. The high dielectric constant has a disadvantageous effect on the speed of signal propagation on the electrical connecting lines which have a high capacitance due to their high dielectric constant. The large capacitance leads to long RC times. The problem of long RC times will become worse in future since, due to the general trend toward ever smaller components, the distances between the individual conductor tracks are continuing to decrease which leads to larger capacitances.
Another problem which accompanies the continuous reduction in size of the electrical circuits is the limited flowability of the doped silicate glasses. As the trenches between the conductor tracks continue to become smaller, this results in voids which are no longer penetrated by the doped silicate glass. The voids have the objectionable characteristic of collecting moisture. During an elevated temperature exposure which the integrated circuit experiences, e.g. when it is soldered on, the integrated circuit explodes due to the vaporization of the collected moisture and, as a result, becomes unusable.
A further disadvantage is the high reflectivity of the doped silicate glass layers which leads to wrong exposures and faulty processing during the subsequent lithographic steps.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method of producing dielectric filling of electrical wiring planes and dielectric filled electrical wiring planes, and a dielectric layer for an electrical wiring plane of an integrated circuit, that overcome the above-mentioned disadvantages of the prior art methods and devices of this general type, and exhibits good filling and reflowing characteristics, a low dielectric constant and reflection-suppressing characteristics in photolithographic steps.
With the foregoing and other objects in view there is provided, in accordance with the invention, an electrically wired integrated circuit, comprising:
a base body;
a conductive layer disposed on the base body and patterned such that it exhibits a first conductor track, a second conductor track, and a trench between the first conductor track and the second conductor track, and
at least one dielectric layer disposed on the conductive layer and at least partially filling the trench, wherein at least one dielectric layer comprises one or more of the polymer materials polybenzoxazole, polynorbornene, polytetrafluoroethylene and their derivatives.
In addition to or alternatively to polybenzoxazole, other materials are also suitable, which can also be applied to a wafer by spin-on methods. These include inorganic materials such as hydrogen silsesquioxane and organic materials such as polybenzoxazole, polyimide, perylene polymers, polynorbornene and polytetrafluoroethylene and their derivatives and especially their fluorinated derivatives.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a process for producing electrical wiring of an integrated circuit comprising the steps of
forming a conductive layer on a base body;
patterning the conductive layer so that a first conductor track, a second conductor track and a trench between the first conductor track and the second conductor track are formed; and
spin-coating at least one dielectric layer of a polymer onto the conductive layer so that the trench is at least partially filled. The polymer comprises polybenzoxazole and/or polynorbornene and/or one of their derivatives.
The preferred polymer material polybenzoxazole (PBO) is distinguished by the fact that it can be applied by spin coating and thus fills the smallest gaps without voids. This prevents cavities which can collect moisture in a HAST (humidity acceleration stress test) test and explode during subsequent elevated temperature steps (popcorn effect). Apart from these excellent planarization characteristics, polybenzoxazole, after having been cured, is distinguished by high temperature stability up to above 400° Celsius and low moisture absorption. Moreover, the dielectric constant of polybenzoxazole in its cured state is less than 3.5. The low dielectric constant makes possible faster signals on the integrated circuit due to the lower parasitic capacitances. Furthermore, polybenzoxazole, due to its absorption characteristics, prevents reflections during subsequent photolithographic exposure steps. As a result, a greatly improved resolution is achieved during subsequent photolithographic steps.
In an advantageous development of the integrated circuit according to the invention, a silicon nitride layer is disposed above at least one dielectric layer. The silicon nitride layer has the advantage that it can be used as passivation layer with excellent blocking effect against water vapor, alkali ions and other substances acting corrosively.
In a further advantageous embodiment of the invention, a silicon oxide layer is disposed between at least one dielectric layer and the silicon nitride layer.
In a further advantageous development of the invention, a photosensitive layer of polybenzoxazole or a photosensitive polyamide is disposed above the first dielectric layer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a dielectric filling of electrical wiring planes, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
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Kirchhoff Markus
Rogalli Michael
Wege Stephan
Dang Phuc T.
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Nelms David
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