Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-02-09
2002-09-24
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S637000, C438S640000
Reexamination Certificate
active
06455410
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing therefore, in particular to a method of manufacturing for a semiconductor device which comprises a wiring structure having contact holes with a large aspect ratio.
2. Description of the Background Art
In recent years the demand for semiconductor devices has been rapidly expanding due to the remarkable spread of information apparatuses such as computers. In addition, semiconductor devices which have a large scale memory capacity and enable high speed operation with respect to function are in high demand. Together with this, a technology relating to a higher integration of semiconductor devices has been developed.
In the following a method of manufacturing for a semiconductor device having a conventional wiring structure is described in reference to
FIGS. 14
to
17
. As shown in
FIG. 14
insulation oxide film
5
and
6
are formed on the main surface of a p-type silicon substrate
1
, which is a semiconductor substrate. A channel region
3
is formed in an active region defined by the insulation oxide film
5
and
6
. A source/drain region
4
is formed in a region in the vicinity of the surface of the channel region
3
. A channel cut impurity region
2
is provided in the lower layer below the channel region
3
and the insulation oxide film
5
and
6
for the purpose of optimizing the impurity concentration of a region beneath the insulation oxide film
5
and
6
so as to increase the insulation characteristics.
An interlayer insulation layer
7
with a three layered structure is formed on the surface of the p-type silicon substrate
1
. This interlayer insulation layer
7
is formed of the first interlayer insulation layer
7
a
comprising a TEOS (Tetra Etyle Ortho Silicate) layer, the second interlayer insulation layer
7
b
comprising a BPSG (Borospho Silicate Glass) layer and the third interlayer insulation layer
7
c
comprising a TEOS layer.
A resist film
8
which has a predetermined aperture pattern is formed on the upper surface of the interlayer insulation layer
7
and a contact hole
10
is formed by using this resist film
8
as a mask for carrying out the etching of the interlayer insulation layer
7
.
Next, as shown in
FIG. 15
, a contact wiring plug
13
with a two layered structure of a barrier metal layer having TiN or TiN/Ti and a tungsten layer is formed after the resist film
8
is removed. After that, as shown in
FIG. 16
, the contact wiring plug
13
which has been formed in the interlayer insulation layer
7
is removed through an etch back method or a CMP (Chemical Mechanical Polishing) method.
Next, as shown in
FIG. 17
, a wiring layer
14
which is connected to the contact wiring plug
13
, and which comprises aluminum or the like in a predetermined form, is formed on the upper surface of the interlayer insulation layer
7
. As described above the source/drain region
4
and the wiring layer
14
are electrically connected by the contact wiring plug
13
provided in the contact hole
10
of the interlayer insulation layer
7
.
In the above described method of manufacturing for a semiconductor device, however, the problems as shown below arise.
First, as described above, a three layered structure of the first interlayer insulation layer
7
a
comprising a TEOS, the second interlayer insulation layer
7
b
comprising a BPSG and the third interlayer insulation layer
7
c
comprising a TEOS is adopted for the interlayer insulation layer
7
.
The reason why the first interlayer insulation layer
7
a
comprising a TEOS is formed on the p-type silicon substrate
1
is that, in the case that a BPSG is used for the second interlayer insulation layer
7
b
which is the middle layer, the impurity which has been doped in this BPSG must be prevented from diffusing into the p-type silicon substrate
1
.
The reason why a BPSG is formed for the second interlayer insulation layer
7
b
is that it is preferable to utilize a material which is rich in fluidity at the time of heat method of manufacturinging order to increase the filling characteristics of the interlayer insulation layer
7
, which is of a three layered structure, and the BPSG has this characteristic.
The reason why a TEOS is formed for the third interlayer insulation layer
7
c
is to increase the tightness of the contact with the resist film.
As a result of the adoption, because of the above described reasons as shown in
FIG. 14
, of the three layered structure for the interlayer insulation layer
7
the second interlayer insulation layer
7
b
is etched larger than the first interlayer insulation layer
7
a
and the third interlayer insulation layer
7
c
at the time of the etching for forming the contact hole
10
due to the difference of the etching rates of the BPSG and the TEOS, which are their etching characteristics and, therefore, a recessed part
10
a
, wherein the side walls are recessed inwardly, is formed on the side walls of the contact hole
10
.
In the case that the contact wiring plug
13
is formed under the condition where the recessed part
10
a
on the side walls of the contact hole
10
is formed, as shown in
FIG. 15
, a hollow area
13
a
is formed in the contact wiring plug
13
. In the case that a wiring layer
14
is formed under the condition where the hollow area
13
a
is formed in the contact wiring plug
13
, as shown in
FIG. 17
no problem arises when a wiring layer
14
is formed in a predetermined position of the third interlayer insulation layer
7
c.
As shown in
FIG. 18
, however, in the case that the first interlayer insulation layer
7
a
and the second interlayer insulation layer
7
b
are removed through etching to a stage where the hollow area
13
a
is exposed in the method of manufacturing for a semiconductor device in conjunction with the peripheral circuits, there are some cases wherein slurry or the like is collected in the hollow area
13
a
, of which the upper part is open, so as to negatively influence the conductive characteristics of the contact wiring plug
13
.
In addition, as shown in
FIG. 19
, in the case that the wiring layer
14
is formed on the area which has been shifted above the contact wiring plug
13
, the hollow area
13
a
is exposed and the etching wet liquid used for the washing process after forming the wiring layer
14
is collected in the hollow area
13
a
so that there is the danger that the wiring area
14
comprising aluminum or the like may be corroded.
SUMMARY OF THE INVENTION
The purpose of this invention is to provide a semiconductor device which will not generate the hollow area in the contact wiring plug formed in the interlayer insulation layer, as well as the method of manufacturing therefore.
The method of manufacturing a semiconductor device according to this invention comprises: the step of the formation of a first conductive region for forming a first conductive region; the step of the formation of an interlayer insulation layer for forming an interlayer insulation layer on said first conductive region; the step of the opening of a contact hole for opening a contact hole which has a recessed region wherein the side walls are recessed in the middle area and which pierces through said interlayer insulation layer and reaches said first conductive region; the step of the formation of a resist film for forming a resist film within said contact hole and on the upper surface of said interlayer insulation layer; the step of the exposure of the recessed region for removing said resist film and part of said interlayer insulation layer located on the upper surface of said interlayer insulation layer so that said recessed region within said contact hole is exposed; the step of the removal of the resist film for removing said resist film of which the residue remains within said second contact hole; the step of the formation of a wiring plug for forming a wiring plug within said contact hole; and the step of the formation of a second wiring region for forming a second wiring r
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Quach T. N.
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