Method of encapsulated copper (Cu) interconnect formation

Details Method of encapsulated copper (Cu) interconnect formation Method of encapsulated copper (Cu) interconnect formation

2001-04-16

2002-09-24

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S623000, C438S638000

Reexamination Certificate

active

06455415

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits and fabrication techniques for forming interconnect structure. More particularly, the present invention relates to integrated circuits and fabrication techniques for forming interconnect structure out of copper. Even more particularly, the present invention relates to integrated circuits and fabrication techniques for encapsulating interconnect structure that has been fabricated out of copper.
BACKGROUND OF THE INVENTION
In semiconductor wafers utilizing multilayered circuits, damascene metal interconnect lines are used to conduct current through the layers using interconnect structure singularly termed a line and a via. A line is also sometimes referred to as a land and a via is sometimes also referred to as a feed-through hole. These interconnect structure were heretofore usually made of aluminum, but are increasingly being made of copper. Currently, semiconductor technology is moving away from the use of aluminum as the metal of choice in circuitry and toward the use of copper. This move toward the production of copper interconnect structure semiconductors is receiving intense research because copper conducts electricity with lower resistance than aluminum which results in increased microprocessor speed. Additionally, copper uses less power and costs less than aluminum. Also, the physical attributes of copper metal allow for space-saving circuitry design. A discussion of the move toward copper in semiconductor devices can be found in “Smokin . . . Watch Out, Fast Computers are on the way Speed is now Pushing Computing Power,” by Andy Maslowski, The Electron, April/May/June 1998, Vol. 25, No.2, pp. 1 and 20.
A published article concerning the challenges to industry in making the move to copper interconnects in integrated circuits and a brief teaching of the fundamentals of copper electroplating is an article entitled “Tantalum, Copper, and Damascene: The Future of Interconnects” by Peter Singer, Semiconductor International, June 1998. The challenges have been accepted by industry, but have resulted in copper interconnect structures that need special encapsulating fabrication techniques to overcome the characteristic that copper diffuses into silicon and silicon dioxide and reacts with most metals and silicides such as Al, Ti, CoSi
2
, NiSi, and TiSi
2
, which are commonly used in microelectronic devices. See “Electroless CoWP Barrier/Protection Layer Deposition For Cu Metallization,” S. Lopatin et al., Material Research Society, 1997, pp. 463-468; “High Aspect Ratio Quarter-micron Electroless Copper Integrated Technology,” Yosi Shacham-Diamand et al., Microelectronic Engineering, 1997, pp. 77-88; and Dubin et al.(U.S. Pat. No. 5,695,810).
U.S. Pat. No. 5,695,810 teaches a technique of encapsulating copper circuit interconnect lines in a CoWP (cobalt-tungsten-phosphide) barrier including a capping step with the CoWP material. Other known fabrication techniques include single-Damascene process, or dual-Damascene process. In the single-Damascene process, either the interconnect lines, or the vias, are fabricated separately, while in the dual-Damascene process, both vias and interconnect lines are fabricated concurrently. The dual-Damascene fabrication process has the limitation of requiring high-k dielectric constant layers that are used to overcome etch-uniformity problems that occur during trench etch fabrication steps. The dual-Damascene fabrication process also has the problem of maintaining adequate seed layer step coverage in designs involving a via or a trench structure whose cross-sectional area has a high aspect ratio (i.e., where the via height to width ratio is at least 3:1). Further, dual-Damascene fabrication problems include concerns about via bottom opening to Cu and cleaning.
Thus, a need exists for an invention which provides an improved semiconductor device having a copper interconnect structure that overcomes undesirable copper diffusion characteristic by using selective electroplated copper fabrication techniques.
A need also exists for an invention which provides an improved semiconductor device having a copper interconnect structure that overcomes undesirable copper diffusion characteristic which is fabricated such that silicon nitride and silicon dioxide layers are not required.
Another need also exists for an invention which provides an improved semiconductor device having a copper interconnect structure that overcomes undesirable copper diffusion characteristic and which is fabricated such that copper interconnect structure in the less than 0.2-&mgr;m range is facilitated.
Yet another need also exists for an invention which provides an improved semiconductor device having a copper interconnect structure that overcomes undesirable copper diffusion characteristic and which is fabricated such that the copper interconnect structure formed by selective electroplated copper fabrication techniques is encapsulate in metal barriers.
Still another need also exists for an invention which provides an improved semiconductor device having a copper interconnect structure that overcomes undesirable copper diffusion characteristic and which is fabricated such that the copper interconnect structure can be formed by with minimal concerns about seed layer step coverage.
BRIEF SUMMARY OF THE INVENTION
Accordingly, and by example only, the present invention addresses the related art needs by providing a method for fabricating a semiconductor device having copper interconnect structure fabricated by a process that comprises the steps of initially forming a blanket copper (Cu) layer formed by electroplating a Cu layer over a semiconductor device which has been previously fabricated to a stage having circuit elements in need of being electrically energized, and or, being electrically coupled to other circuit elements to perform an electronic function of the semiconductor device. By example, in formation of a copper via interconnect structure, a blanket of electroplated Cu layer structure is fabricated over a low dielectric constant material (referred to herein as low K
1
material) such as poly(arylene ether) (“PAE”), fluorinated aromatic ether (“FLARE”), fluorinated polyimide (“FPI”), benzocyclobutene (“BCB”), hydrogen silsesquioxane (“HSQ”), methyl silsesquioxane (“MSQ”), xerogel, and fluorinated glass. The low K
1
dielectric layer has previously undergone a photolithographic process and comprises at least one via for forming an interconnect structure. The via's sidewalls and the surface of the low K
1
dielectric layer structure further comprise a metal barrier layer, such as tantalum (Ta), tantalum nitride (TaN) and tungsten nitride WN, fabricated such that the metal barrier covers the surface and extends into the via to form a sidewall liner structure.
Using Cu chemical vapor deposition and/or Cu electroplating techniques, a substantially thin (≦0.25 &mgr;m) blanket of copper is formed to cover the metal barrier surface and also fill the metal barrier-lined via structure. It should be emphasized that the filled via structure is also substantially thin (≦0.25 &mgr;m). A photoresist layer is then fabricated over the electroplated Cu layer and then by means of a photolithographic process, and by example only, a trench structure, is formed overlying the previously Cu-filled via structure. The trench structure is selectively Cu electroplated such that it is substantially thicker than the previously Cu-filled via structure (>>0.25 &mgr;m) and bonds with the previously Cu-filled underlying via structure. After the photoresist is removed, an electropolishing step, or etching step removes the substantially thin blanket of copper formed on the metal barrier surface and shapes the bonded Cu-electroplated via-trench structure.
The electropolishing step, or etching step, is further controlled to stop at the metal barrier on the surface of the low K
1
material to assure that a metallic interface exists for the subsequent metallic capping step. In forming the metallic barrier cap and by contro

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