DRAM memory cell and array having pass transistors with...

Details DRAM memory cell and array having pass transistors with... DRAM memory cell and array having pass transistors with...

1999-02-01

2002-05-07

Flynn, Nathan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

30, 30

Reexamination Certificate

active

06384439

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor devices, and more particularly to dynamic random access memory (DRAM) storage cells and arrays.
BACKGROUND OF THE INVENTION
As the complexity and power of computing systems increases, the amount of memory required for systems has also increased. This has resulted in the drive for semiconductor memory devices of increased storage capacity. At the same time, the desire for more efficient manufacturing and more compact electronic devices, has led to the competing interest of shrinking semiconductor memory devices to as small a size as possible.
A common type of semiconductor memory device is the dynamic random access memory (DRAM). DRAMs typically include a large number (millions or thousands) of memory cells, each of which can store at least one bit of data. The memory cells are usually arranged into an array configuration of rows and columns. Because the primary function of DRAM is to store data, the DRAM array makes up the majority of the area on a DRAM. Thus, any reduction in the size of a memory cell translates into reduced array size, and hence a smaller overall DRAM. Furthermore, a smaller memory cell allows more information to be stored in a given amount of area, leading to larger capacity DRAMs.
One reason for the increase in system computing power is the faster speeds at which such systems operate. For this reason, it is also desirable to provide a DRAM that has a fast operating speed, in order to provide data at a sufficient rate to a system. Another important aspect of DRAM operation arises from the fact that DRAMs are being used more often in battery operated applications, such as laptop computers. Thus, the rate of power consumption is an important feature of a DRAM. Lower power DRAMs can contribute to longer battery lifetimes in battery operated systems.
A typical DRAM array includes memory cells within the same row being commonly coupled to a word line, while memory cells within the same column are commonly coupled to a bit line. The data stored within the memory cells can be accessed according to various DRAM operations such as read operations, write operations and refresh operations. A memory cell access operation will usually begin with the application of an external memory address, resulting in the activation of a word line. Once activated, the word line couples the data stored within its respective row to the bit lines of the array.
The coupling of memory cells to bit lines results in differential voltage signals appearing on the bit lines (or bit line pairs). The differential signals are relatively small, and so must be amplified (usually by a sense amplifier), resulting in amplified data signals on the bit lines. The applied memory address also activates column decoder circuits, which connect a given group of bit lines to input/output circuits. Commonly, the memory address is multiplexed, with a row address being applied initially to select a word line, and a column address being applied subsequently to select the group of bit lines.
The typical DRAM memory cell stores data by placing charge on, or removing charge from, a storage capacitor. Once a storage capacitor has been initially charged, over time, the amount of charge will be reduced by way of a leakage current. Thus, it is important for the DRAM to restore the charge on the capacitor before the amount of charge falls below a critical level, due to leakage mechanisms. Restoration of charge is accomplished with a refresh operation.
The critical level of charge for a storage capacitor arises out of the minimum sensitivity of the DRAM sense amplifiers. The storage capacitor must have enough charge to create a sufficient differential voltage on the bit lines for the sense amplifier to reliably sense. The time needed before the charge on the capacitor falls below the critical level is commonly referred to as the maximum “pause” period. A DRAM must perform a refresh operation on every row in the device before that row experiences the maximum “pause” period, without having its cells refreshed by way of a refresh operation, read operation, or a write operation.
The refreshing operation of a DRAM consumes a relatively large amount of power. Minimizing the power used for refresh is thus a desirable goal. One way to reduce refresh power consumption is to reduce the rate of charge leakage from the storage capacitor. This increases the maximum pause period, allowing refresh operation to occur with less frequency.
Referring now to
FIG. 1
, a prior DRAM array is set forth and designated by the general reference character
100
. The DRAM array
100
is arranged as an n×m array, having n rows coupled to n word lines (WL
0
-WLn) and m sets of bit line pairs (BL
0
, BL
0
_-BLm, BLm_). A memory cell is formed where a word line intersects a bit line pair. The memory cells are designated as M
00
-Mnm, where the first digit following the “M” represents the physical row of the memory cell's location, and the second digit represents the physical column of the memory cell's location. For example, M
00
is the memory cell located at the intersection of WL
0
and bit line pair BL
0
/BL
0
_. Each memory cell (M
00
-Mnm) contains a pass transistor (shown as n-channel MOSFETs Q
00
-Qnm) and a storage capacitor (shown as C
00
-Cnm).
The word lines of the DRAM array
100
are driven by a word line driver bank
102
coupled to the word lines (WL
0
-WLn). In addition, a sense amplifier bank
104
is coupled to the bit line pairs (BL
0
, BL
0
_-BLm, BLm_). The word line driver bank
102
is separated into n separate word line driver circuits, shown as DRV
0
-DRVn. The word line driver bank
102
is responsive to a row address (not shown) in such a manner, that only one word line driver circuit (DRV
0
-DRVn) will drive its corresponding word line high when the row address received. For example, word line driver circuit DRV
0
will drive word line WL
0
high when the row address value of “zero” is received, and word line driver circuit DRVn will drive word line WLn high when the row address value of “n” is received.
The sense amplifier bank
104
is separated into m separate sense amplifier circuits, shown as SA
0
-SAm. While all of the sense amplifiers
104
will be activated simultaneously, only selected of the sense amplifiers (SA
0
-SAm) will pass its sensed data to the DRAM outputs (not shown). A sense amplifier (SA
0
-SAm) will be selected according to the column address (not shown) applied to a column decoder (also not shown) in the DRAM.
As noted previously, data is stored in the DRAM array
100
by placing or removing charge from the storage capacitors (C
00
-Cnm). Each memory cell (M
00
-Mnm) is shown to further include a storage node
106
-
112
formed at the junction of the source of the pass transistor (Q
00
-Qnm), and its associated storage capacitor (C
00
-Cnm). The potential at the storage node will determine the logic of the data stored within the memory cell. A memory cell (Q
00
-Mnm) is accessed by coupling its storage node (
106
-
112
) to its respective bit line (BL
0
, BL
0
_-BLm, BLm_).
In a write cycle, a row address is applied to the DRAM and will activate a word line. If it is assumed that a logic value “1’ is to be written into memory cell M
00
, word line driver circuit DRV
0
will raise word line WL
0
to a high voltage level. A column address will couple write circuitry (not shown) to bit line BL
0
to allow a high logic level to be written into storage cell M
00
. The high logic level will be stored in memory cell M
00
at storage node
106
by placing charge on storage capacitor C
00
. In order to ensure maximum charge is placed on the storage capacitor, word line driver circuit DRV
0
will raise word line WL
0
to a voltage level that is at least one n-channel threshold voltage (Vtn) above the voltage level applied to bit line BL
0
during the write cycle.
Once the storage node
106
reaches a high logic level, which is typically equal to the high power supply voltage (Vcc) of the DRAM array
100
, the DRAM is allowe

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