Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1999-10-08
2002-08-27
Kim, Kenneth S. (Department: 2783)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C712S024000, C712S204000, C713S300000, C717S141000
Reexamination Certificate
active
06442701
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to microprocessors, and more particularly to methods of using programming instructions in a manner that reduces the power dissipation of a processor.
BACKGROUND OF THE INVENTION
Power efficiency for processor-based equipment is becoming increasingly important as people are becoming more attuned to energy conservation issues. Specific considerations are the reduction of thermal effects and operating costs. Also, apart from energy conservation, power efficiency is a concern for battery-operated processor-based equipment, where it is desired to minimize battery size so that the equipment can be made small and lightweight. The “processor-based equipment” can be either equipment designed especially for general computing or equipment having an embedded processor.
From the standpoint of processor design, a number of techniques have been used to reduce power usage. These techniques can be grouped as two basic strategies. First, the processor's circuitry can be designed to use less power. Second, the processor can be designed in a manner that permits power usage to be managed.
On the other hand, given a particular processor design, its programming can be optimized for reduced power dissipation. Thus, from a programmer's standpoint, there is often more than one way to program a processor to perform the same function. For example, algorithms written in high level programming languages can be optimized for efficiency in terms of time and power. Until recently, at the assembly language level, most optimization techniques have been primarily focussed on speed of execution without particular regard to power use.
The programmer's task of providing power efficient code can be performed manually or with the aid of an automated code analysis tool. Such a tool might analyze a given program so to provide the programmer with information about its power usage information. Other such tools might actually assist the programmer in generating optimized code.
U.S. Pat. No. 5,557,557, to Franz, et al., entitled “Processor Power Profiler”, assigned to Texas Instruments Incorporated, describes a method of modeling power usage during program execution. A power profiler program analyzes the program and provides the programmer with information about energy consumption. A power profiler is also described in U.S. patent application Ser. No. 06/046,811, to L. Hurd, entitled “Module-Configurable, Full-Chip Power Profiler”, assigned to Texas Instruments Incorporated.
Once the power requirements of a particular program are understood, the code can be optimized. Automating this aspect of programming requires a code generation tool that can restructure computer code, internal algorithms as well as supporting functions, for minimum power usage.
SUMMARY OF THE INVENTION
One aspect of the invention is a method of optimizing computer programs for power usage. The method is useful for various types of processors that execute “multiple-instruction words” (as defined herein). Examples of such processors are VLIW (very long instruction word) processors and dual datapath processors.
Multiple-instruction words are characterized by having “slots”, each word having a different slot for each instruction. Thus, slot
1
contains the first instruction of each word, slot
2
the second, etc. Typically, each word is executed in its own processor cycle, but this is not necessarily the case.
For a particular listing of program code, the syntax of any series of two or more words is compared. It is determined whether, from word to word, one or more NOP instructions can be moved to the same slot without substantially affecting functionality of the program code. If not, the words are modified by moving the NOP instructions to the same slot and making any other modifications necessary to maintain the same functionality. As a result, the NOP instructions are aligned in the same slot. The code is further modified such that during fetch cycles for these aligned instructions, access to memory storing them may be disabled.
Thus, optimization is achieved at the processor architecture level, rather than to high level programming. This permits a processor to be programmed in a manner that is most efficient for that processor. The method can be easily adapted to the characteristics of the processor and its instruction set.
REFERENCES:
patent: 5495617 (1996-02-01), Yamada
patent: 5557557 (1996-09-01), Frantz et al.
patent: 5584031 (1996-12-01), Burch et al.
patent: 5787302 (1998-07-01), Hampapuram et al.
patent: 5790877 (1998-08-01), Nishiyama et al.
Brady III W. James
Kim Kenneth S.
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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