Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-02-07
2002-07-02
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S229000
Reexamination Certificate
active
06414894
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly to reduction of current consumption in standby state of a semiconductor device having therein a dynamic semiconductor memory device requiring refresh.
2. Description of the Background Art
Recently, as personal digital assistants have widely been used, a semiconductor memory device is required to have smaller size and lower power consumption. The semiconductor memory device is often employed being integrated on one chip with a microcomputer and a large-sized logic circuit. An integrated circuit on which various circuits of such large size are mounted to implement system-on-chip is herein referred to as system LSI.
A conventional structure of a semiconductor memory device is first described before discussion on reduction in supply current consumption of the system LSI.
FIG. 35
is a schematic block diagram showing a structure of a conventional semiconductor memory device
1000
.
Referring to
FIG. 35
, semiconductor memory device
1000
includes an external clock signal input terminal
1116
receiving externally supplied complementary clock signals ext.CLK and ext./CLK, clock input buffers
1084
and
1085
buffering the clock signals supplied to external clock signal input terminal
1116
, an internal control clock signal generating circuit
1118
receiving respective outputs of clock input buffers
1084
and
1085
to generate internal clock signal int.CLK, and a mode decoder
1120
receiving an external control signal supplied to an external control signal input terminal
1110
via input buffers
1012
-
1020
which operate according to internal clock signal int.CLK.
External control signal input terminal
1110
receives clock enable signal CKE, chip select signal /CS, row address strobe signal /RAS, column address strobe signal /CAS and write control signal /WE.
Clock enable signal CKE is used to allow a control signal to be input to the chip. If this signal is not activated, input of the control signal is not permitted and semiconductor memory device
1000
does not accept signal input from the outside.
Chip select signal /CS is used for determining whether a command signal is input or not. When this signal is activated (at L level), a command is identified according to a combination of levels of other control signals at the rising edge of the clock signal.
Mode decoder
1120
outputs an internal control signal for controlling an operation of an internal circuit of semiconductor memory device
1000
according to these external control signals. Mode decoder
1120
outputs, as internal control signals, signal ROWA, signal COLA, signal ACT, signal PC, signal READ, signal WRITE, signal APC and signal SR.
Signal ROWA indicates that row-related access is made, signal COLA indicates that column-related access is made, and signal ACT is used to instruct that a word line is activated.
Signal PC specifies precharge operation to end a row-related circuit operation. Signal READ instructs a column-related circuit to perform reading operation, and signal WRITE instructs the column-related circuit to perform writing operation.
Signal APC specifies auto precharge operation. When the auto precharging operation is designated, precharge operation is automatically started simultaneously with the end of a burst cycle. Signal SR designates self refresh operation. When the self refresh operation starts, a self refresh timer operates. After a certain time passes, a word line is activated and the refresh operation starts.
Semiconductor memory device
1000
further includes a self refresh timer
1054
which starts its operation when self refresh mode is designated by signal SR and then designates activation of a word line, i.e., start of the refresh operation when a certain time passes, and a refresh address counter
1056
for generating a refresh address according to an instruction from self refresh timer
1054
.
Semiconductor memory device
1000
further includes a reference potential input terminal
1022
receiving signal VREF which is to be used as a reference for determining whether an input signal is H or L level, a mode register
1046
holding an address signal supplied via an address signal input terminal
1112
as well as information regarding a predetermined operation mode, for example, information regarding burst length according to a combination of external control signals described above, a row address latch
1250
receiving address signals via address input buffers
1032
-
1038
operating according to internal clock signal int.CLK
2
to hold, when a row address is input, the input row address, a column address latch
1550
receiving address signals A
0
-A
12
to hold, when a column address is input, this column address, a multiplexer
1058
receiving respective outputs from refresh address counter
1056
and row address latch
1250
to select the output from row address latch
1250
in the normal operation and select the output from refresh address counter
1056
in self refresh operation and accordingly output the selected one, and a row predecoder
1136
receiving an output from multiplexer
1058
to predecode a row address.
Semiconductor memory device
1000
further includes a burst address counter
1060
generating an internal column address according to burst length data from mode register
1046
based on the column address held in column address latch
1550
, a column predecoder
1134
receiving an output of burst address counter
1060
to predecode a corresponding column address, a bank address latch
1052
receiving bank addresses BA
0
-BA
2
supplied to an address input terminal via input buffers
1040
-
1044
which operate according to internal clock signal int.CLK, and a bank decoder
1122
receiving an output of bank address latch
1052
to decode a bank address.
The address signal supplied to address signal input terminal
1112
is also used for writing data in the mode register by a combination of any bits when operation mode information is written into the mode register. For example, burst length BL, value of CAS latency CL and the like are designated by a combination of a predetermined number of bits of an address signal.
Bank address signals BA
0
-BA
2
designate an access bank in each of the row-related access and the column-related access. Specifically, in the row-related access and the column-related access each, bank address signals BA
0
-BA
2
supplied to address signal input buffers
1040
-
1044
are taken by bank address latch
1052
and then decoded by bank decoder
1122
to be transmitted to each memory array block (bank).
In addition, semiconductor memory device
1000
includes memory array blocks
100
a
-
100
g
respectively serving as banks
0
-
7
each for independent reading/writing operation, a row decoder
1244
for selecting a row (word line) in a corresponding bank according to respective outputs from bank decoder
1122
and row predecoder
1136
, a column decoder
1242
for selecting a column (bit line pair) in a corresponding bank according to an output from column predecoder
1134
, an I/O port
1266
supplying data read from a selected memory cell in a selected bank to a global I/O bus G-I/O in reading operation and supplying write data transmitted by bus G-I/O to a corresponding bank in writing operation, a data input/output circuit
1086
holding externally supplied write data and supplying it to bus G-I/O in writing operation and holding read data transmitted by bus G-I/O in reading operation, and bidirectional input/output buffers
1072
-
1082
for transmitting input/output data DQ
0
-DQ
31
between data input/output circuit
1086
and data input/output terminal
1070
.
Bidirectional input/output buffers
1072
-
1082
operate in synchronization with the internal clock signal according to operation mode data held in mode register
1046
.
FIG. 36
illustrates power supply potential applied from the outside to a conventional system LSI.
Referring to
FIG. 36
, the system LSI includes a chip CH on which a logic p
Hidaka Hideto
Ishikawa Masatoshi
Kato Hiroshi
Ooishi Tsukasa
Tsuji Takaharu
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