Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-02-09
2002-06-11
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
Reexamination Certificate
active
06403979
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to a method of measuring the effective channel length of a transistor, and a test structure for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background,
FIG. 1
depicts an illustrative prior art transistor
10
formed above a semiconducting substrate
11
. The transistor
10
is generally formed in an active region
23
of the substrate
11
as defined by trench isolation regions
24
. The transistor
10
is generally comprised of a gate insulation layer
13
, a gate electrode
14
, sidewall spacers
15
, and source/drain regions
16
. The gate electrode
14
also has a length, as indicated by the dimension
21
. The various components of the transistor
10
shown in
FIG. 1
, as well as the methods of making such components, are well-known to those skilled in the art and will not be repeated in greater detail herein. At the point of fabrication depicted in
FIG. 1
, a layer of insulating material
17
and a plurality of conductive plugs
18
that are electrically coupled to the source/drain regions
16
have been formed above the transistor
10
.
In modern semiconductor devices, an important parameter of transistor devices is the effective channel length (L
eff
) of the device. For example, the effective channel length of a transistor has a great impact on a variety of device performance characteristics, e.g., the switching speed of the transistor, leakage currents, etc. In general, the effective channel length is defined as the distance between the source/drain regions
16
, as indicated by the arrow
12
in FIG.
1
. As shown in
FIG. 1
, the source/drain regions
16
extend somewhat under the sidewalls
20
of the gate electrode
14
. The combined amount of this source/drain encroachment under the sidewalls
20
is generally referred to in the industry as “&Dgr;L.” The effective channel length for a transistor may be determined by subtracting the &Dgr;L value from the length
21
of the gate electrode
14
(L
eff
=Gate Length−&Dgr;L).
A variety of techniques are employed in the industry in attempts to calculate or determine the effective channel length of a transistor. Some of those techniques involve applying a voltage across the source/drain regions
16
, via conductive plugs
18
, and employing a test instrumentation device
19
to measure a resistance of the channel region of the transistor
10
. During the course of forming a transistor, a variety of dopant materials are implanted into the channel region of the transistor
10
. For example, the channel region of a typical transistor may be subjected to threshold voltage implants, punch-through voltage implants, and so-called halo implants to achieve one or more desired effects on the resulting transistor. Unfortunately, it is believed that such heavy doping schemes lead to erroneous results from conventional transistor-based algorithms for calculating the effective channel length of the device, which make many assumptions about things such as channel doping levels and uniformity erroneous.
The present invention is directed to a method that may solve, or at least reduce, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to a method of measuring the effective channel length of a transistor, and a test structure for accomplishing same. In one illustrative embodiment, the structure is comprised of a first resistor comprised of a first doped region formed in a semiconducting substrate between a first pair of spaced-apart structures positioned above the substrate, the first resistor having a first width defined by the spacing between the first pair of structures, and a second resistor comprised of a second doped region formed in the substrate between a second pair of spaced-apart structures positioned above the substrate, the second resistor having a second width defined by the spacing between the second pair of structures. In the test structure, the width of the second resistor is greater than the width of the first resistor. The test structure further comprises a plurality of conductive contacts electrically coupled to each of the first and second doped regions. In another illustrative embodiment, the width of the second resistor is at least 1.5 times the width of the first resistor.
In one embodiment, the method disclosed herein comprises forming a first resistor comprised of a first doped region formed in a semiconducting substrate between a first pair of spaced-apart structures positioned above the substrate, the first resistor having a first width defined by the spacing between the first pair of structures, forming a second resistor comprised of a second doped region formed in the substrate between a second pair of spaced-apart structures positioned above the substrate, the second resistor having a second width defined by the spacing between the second pair of structures, the second width being greater than the first width, and forming a plurality of conductive contacts that are electrically coupled to each of the first and second doped regions. The method further comprises determining a resistance for each of the resistors by performing a process that at least comprises applying a voltage across the doped region of each of the first and second resistors, calculating, based upon the determined resistance of the first and second resistors, a &Dgr;w value that corresponds to an amount of lateral encroachment of each of the doped regions under the spaced-apart structures, and determining an effective channel length for a transistor by subtracting the determined &Dgr;w value from the length of a gate electrode of the transistor. In one particularly illustrative embodiment, the &Dgr;w value may be calculated in accordance with the following equation: &Dgr;w=(R
1
W
1
−R
2
W
2
)/(R
1
−R
2
).
REFERENCES:
patent: 5895960 (1999-04-01), Fritz et al.
D.S. Perloff, “A Van Der Pauw Resistor Structure for Determining Mask superposition errors on semiconductor slices” in Solid State Electronics, Aug. 21, 1978, vol. 21, pp. 1013-1018.
Cheek Jon D.
Kadosh Daniel
Advanced Micro Devices , Inc.
Dickey Thomas
Tran Minh Loan
Williams Morgan & Amerson P.C.
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