Electrical computers and digital data processing systems: input/ – Interrupt processing – Programmable interrupt processing
Reexamination Certificate
1999-03-22
2002-06-04
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
Programmable interrupt processing
C709S241000
Reexamination Certificate
active
06401155
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to thread-oriented processing and, in particular, to multiple-thread processing by the use of contexts.
2. Description of Related Art
In multiple-thread processing, a processor is capable of successively running a plurality of different processes (commonly referred to as “threads”). Upon the occurrence of a particular event, such as after the elapse of a predetermined time period or upon the receipt of a specific instruction, the processor suspends running of one thread, stores a context describing the status of the thread being suspended, and begins running another thread, which is also described by a respective context. Each “context” contains information needed for the processor either to initiate running of a new thread or to continue operation of a suspended thread. Typically this information includes memory addresses, status information and data.
In order to provide direct and rapid access to stored thread contexts, some processors include multiple banks of local context registers. This, however, is an inflexible arrangement which limits to a fixed quantity the number of threads that can be run. It is also inefficient whenever the number of threads is smaller than the number of register banks provided.
Alternatively, the multiple contexts can be stored in a separate memory. Various examples of such an approach are described in U.S. Pat. No. 5,349,680. In one of these examples, described in the patent as a conventional information processing apparatus, a main processor includes both an application supporting unit for successively executing operations from different application processes and a system supporting unit for controlling the operation in the information processing apparatus. The efficiency of this arrangement is described as inferior, because the application supporting unit and the system supporting unit are never operated at the same time. U.S. Pat. No. 5,349,680 proposes alternative arrangements utilizing multiple stored contexts, but each of these arrangements requires the use of two separate processors. This is an expensive way to improve efficiency.
SUMMARY OF THE INVENTION
It is an object of the invention to enable rapid and efficient multiple-thread processing by a single processor that does not suffer from the inflexibility of utilizing a fixed number of local context registers.
This and other objects are achieved by swapping contexts between a context register set and a memory. This enables rapid multiple-thread processing with a minimum of hardware. In accordance with the invention, a method is employed which includes:
associating each of the interrupts with a respective memory location;
storing in the memory locations a plurality of respective thread context pointers, each of the pointers identifying a memory location for containing a thread context fully describing the operational status of one of the threads;
in response to the occurrence of any of the interrupts, reading the pointer from the respective memory location associated with the interrupt;
from the memory location identified by the thread context pointer, reading the respective thread context into the context register set; and
running the thread described by the thread context read.
By storing in memory locations associated with respective interrupts not contexts themselves, but pointers to contexts, the interrupts are de-referenced from specific contexts. This provides a high degree of versatility in determining responses to interrupts. It also enables memory to be conserved by storing in only one memory location a context which is common to more than one interrupt and by including the address of this common context in each of the pointers for these interrupts. Further, by storing contexts themselves directly in the memory locations identified by the pointers, rapid processor changes from one thread to another are made possible.
Note that the word “memory”, as used herein, is intended to be interpreted as generally as is consistent with the manner in which it is used and includes, without limitation, volatile and non-volatile devices of various types, such as registers, RAMs, DRAMs, ROMs, and combinations of such devices. Additionally, “reading” means retrieving information from one memory and writing it into another.
In a particularly advantageous embodiment of the invention, certain instructions in a program stream (i.e. the instruction sequence that forms the program) being executed by the processor directly effect context changes in the processor. This enables rapid context changes to be initiated by the threads themselves.
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Ross Kevin
Saville Winthrop L.
Auve Glenn A.
Philips Electronics North America Corporation
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