Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1998-06-08
2002-04-30
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S758000
Reexamination Certificate
active
06380554
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a test structure from which electrical measurements may be taken to determine overlay, or the degree of misalignment between successive layers of conductors in the integrated circuit.
2. Description of the Related Art
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions (e.g., source/drain regions) have been placed within a silicon-based substrate and gate areas defined upon the substrate, an interlevel dielectric is formed across the topography to isolate the gate areas and the impurity regions. Interconnect routing is then placed across the semiconductor topography and connected to the impurity regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. The entire process of making ohmic contacts to the impurity regions and/or the gate areas and routing interconnect material between the ohmic contacts is described generally as “metallization”. As the complexity of integrated circuits has increased, the complexity of the metallization composition has also increased. Conductive materials other than metal are commonly used for metallization. As such, the term metallization is generic in its application.
A local interconnect is a special form of interconnect used to connect structures which are spaced a relatively short distance apart.
FIG. 1
depicts a partial top plan view of an exemplary integrated circuit employing a local interconnect. A pair of transistors
10
and
12
are arranged a lateral spaced distance apart upon and within a semiconductor substrate. Transistors
10
and
12
comprise respective gate conductors
14
and
16
interposed between respective source/drain regions
18
and
20
. Those source/drain regions
18
and
20
are arranged within the substrate and are isolated from each other by field isolation regions. A local interconnect
22
extends across the substrate from gate conductor
14
of transistor
10
to one source/drain region
20
of transistor
16
. The local interconnect
22
is oriented such that it does not pass over source/drain regions
18
and cause unwanted shorting between gate conductor
14
and source/drain regions
18
. Using a local interconnect to couple a gate of one transistor to a source/drain region of another transistor is prevalent in, for example, high density VLSI logic and SRAMs. Local interconnects, when covered with a dielectric, permit “global” interconnect to extend in an unrestricted manner a dielectric-spaced distance over the local interconnects.
Global interconnects and local interconnects are typically formed above a semiconductor topography by one of two methods. In the so-called damascene process, the conductive material from which an interconnect is made is deposited into a trench which has been etched into an interlevel dielectric. Alternatively, the conductive material may be deposited across an interlevel dielectric, and select portions of the conductive material may be etched away to define the interconnect. Whatever the method used to form a local interconnect, a technique known as “lithography” is generally used to define the regions of the interlevel dielectric or conductive material to be etched. Lithography entails transferring an optical image to a photosensitive film from a patterned mask plate (i.e., reticle) placed in proximity to the film. The photosensitive film, i.e., “photoresist” has two main properties. First, solubility of the resist changes in response to it being exposed to appropriate radiation. Second, a hardened resist is resistant to attack by an etchant capable of removing selectively exposed conductive and/or dielectric material.
The mask plate is patterned such that it includes both transparent and opaque regions. Patterns upon the mask plate are projected onto the resist using various forms of radiation. Ultraviolet light is the primary form of radiation that is used, but x-rays and electron beams are growing in popularity. The radiation is transmitted through only the transparent portions of the mask plate to the resist. The resist solubility of regions that are exposed to radiation is altered by a photochemical reaction. A solvent may be used to remove the resist areas of higher solubility. If the resist is a positive resist, the resist areas exposed to radiation are removed. On the other hand, if the resist is a negative resist, the unexposed resist areas are removed while the exposed areas are retained. Once the resist is patterned, regions of the conductive material or dielectric not covered by the resist are etched. Finally, the resist is removed, leaving a duplicate of the mask plate pattern etched into the substrate film.
During lithography, it is necessary that the mask plate pattern be properly aligned relative to previously formed features in the topography. Typically, alignment is performed using a structure known as an “alignment mark”. The alignment mark includes an alignment target that is formed in a layer of the topography. An alignment guide formed within the mask plate can then be visually or optically aligned with the alignment mark. Alignment is achieved by moving the mask plate until the alignment guide and the alignment target are correctly positioned with respect to each other. Perfect alignment of the patterned topography to the desired image to be printed is rarely achieved.
Proper lithographic alignment is necessary to avoid failure of devices employed by an integrated circuit. For instance, if local interconnect
22
in
FIG. 1
is patterned such that it is shifted to the right of its targeted position, it may inadvertently couple gate conductor
14
to gate conductor
16
. In the extreme, lithographic misalignment may lead to shorting between structures that should be isolated from each other and isolation of structures that should be coupled to each other. Even if the extreme scenario does not occur, the contact resistance between successive layers of conductors may be increased if they are slightly misaligned. Consequently, devices may receive less voltage or current than desired.
To ensure that a lithographic system is performing accurate alignment during fabrication, the overlay, i.e., the degree of misalignment between successive layers of patterns formed in a semiconductor topography, may be measured. Generally, a test structure comprising features, such as successive layers of conductors, is formed upon a wafer, along with other test structures and/or with functioning integrated circuit devices. The distances between the features of the test structure are measured to determine the extent by which the features are shifted from their desired or targeted locations. Such measurements are often performed using an optical measurement system such as a scanning electron microscope (“SEM”). Unfortunately, taking those types of measurements are often time consuming. Further, accuracy of measurements made using an optical measurement system may be limited by the resolution of the system or ability of the system to distinguish closely spaced objects.
It would therefore be of benefit to develop a test structure and method which would provide for more rapid and accurate determination of the overlay between successive layers of conductors. That is, it would be desirable if the method used to find the overlay does not rely on measurements taken using an optical measurement system. Such a test structure and method would prove beneficial in possibly locating the source of misalignment, and would therefore allow for corrective measures to be taken to prevent future misalignment problems. To be a viable test structure, it is desired that it not only quantify misalignment, but also indicate the direction of misalignment. Quantifying the amount and direction of misalignment provides indicia to an operator necessary for him or her to adjust for the misalignment on future wafer runs.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved b
Bush John J.
Fulford Jr. H. Jim
Gardner Mark I.
Cao Phat X.
Conley & Rose & Tayon P.C.
Daffer Kevin L.
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