Dual trench isolation for a phase-change memory cell and...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S002000, C257S110000, C257S121000, C257S124000, C257S192000, C257S246000, C257S295000, C257S296000, C257S300000, C257S350000

Reexamination Certificate

active

06437383

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase-change memory device. More particularly, the present invention relates isolation of the memory device. In particular, the present invention relates to a phase-change memory device with minimum feature size.
2. Description of Related Art
As microelectronic technology progresses, the need has arisen for new data retention schemes. One such data retention scheme is the chalcogenide phase-change technology. Typically, a phase-change memory device includes a lower electrode, also known as a “matchstick”. The lower electrode may be polysilicon, metal, or a metal compound such as a metal nitride.
One challenge of forming a lower electrode in a phase-change memory cell is to shrink the cell size while not losing increasing cross-talking between a given memory cell and a neighboring memory cell.
After the formation of a recess in a substrate that exposes an active area, a conformal introduction of lower electrode material is required. Lower electrode material is typically any electrically conductive or semiconductive material such as polycrystalline silicon, metal, or metal compound. The conformal introduction of lower electrode material that is polycrystalline silicon may follow conventional introduction techniques known to those skilled in the art including chemical vapor deposition (CVD) techniques. Thereafter, a dopant is introduced into the polycrystalline silicon to adjust the resistivity, in one aspect, to lower the resistivity of the material. A suitable dopant is a P-typed dopant such as boron introduced. From the combination of polysilicon and dopant, a silicidation process is required to form a silicide of the lower electrode. This process typically is a doping, a first anneal, a wet strip, and a second anneal.
After proper doping and fill into the trench, a planarization step is required to remove any horizontal component of the lower electrode. Thereafter, a modifier material must be introduced into a portion of the lower electrode material to combine and/or react with the lower electrode material near the top to form a different material. The formation of a different material also prepares the top of the matchstick to form suitable ohmic contact with the phase-change material. The modifier is introduced to raise the local resistance of the lower electrode material. By modifying a portion of the lower electrode material, the resistivity at that modified portion may be changed. Because the modifying material is of a higher resistivity, the lower electrode may not provide sufficiently suitable ohmic contact between the lower electrode and the volume of memory material for a desired application. In such cases, modifying material may be introduced into the lower electrode at a depth below the exposed surface of the lower electrode. For example, a lower electrode of polycrystalline silicon may have polycrystalline silicon at the exposed surface and a modifying material at a depth below the exposed surface. Additionally, barrier materials must be added to prevent cross-contamination between the chalcogenide material and the lower electrode.


REFERENCES:
patent: 6087674 (2000-07-01), Ovshinsky et al.
patent: 6165836 (2000-12-01), Forbes et al.

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