Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-02
2002-06-04
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S374000, C438S259000
Reexamination Certificate
active
06399985
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device having a field effect element and a method for manufacturing the same.
2. Description of the Background Art
Semiconductor integrated circuits have increased the tendency of high density and have achieved high speed operation and low voltage of power supply at the same time. Especially in advanced integrated logical circuits such as MPUs (micro processing units), in order to achieve these at the same time, the transistor performance has been increased and the current driving capability per channel width, i.e., unit area, has been enhanced.
A transistor having high current driving capability can obtain a sufficient output current in a smaller area, thus allowing for high integration.
In the meanwhile, still higher integration has been achieved by employing trench isolation as an element isolation means for electrically isolating a large number of elements. The trench isolation is a technique of electrically isolating elements by filling a trench disposed therebetween with an insulator. Recent advances in the technology of burying have made it possible to form a narrower and deeper element isolation insulating film.
FIG. 29
illustrates, in plan view, the construction of a semiconductor device
80
in which elements are electrically isolated from each other by trench isolation. Specifically,
FIG. 29
is a fragmentary view when the semiconductor device
80
is seen from the top of its semiconductor substrate, and illustrates an arrangement of two MOS field effect transistors (hereinafter referred to as MOS transistors) M
1
and M
2
.
The MOS transistors M
1
and M
2
are each surrounded by a trench isolation oxidation film and are electrically isolated from each other, and these are also electrically isolated from other semiconductor elements (not shown).
As shown in
FIG. 29
, the MOS transistor M
1
has a larger channel width than the MOS transistor M
2
, and it comprises an elongated ate electrode
31
and a pair of source/drain regions
11
disposed in the semiconductor substrate surface located outside of the transversely opposite sides of the gate electrode
31
. The gate electrode
31
at one end portion in the longitudinal direction is connected via a contact plug
51
to a wiring layer
61
. The source/drain regions
11
are each connected via a plurality of contact plugs
511
to a wiring layer
611
.
The MOS transistor M
2
has an elongated gate electrode
32
and a pair of source/drain regions
12
disposed in the semiconductor substrate surface located outside of the transversely opposite sides of the gate electrode
32
. The gate electrode
32
at one end portion in the longitudinal direction is connected via a contact plug
52
to a wiring layer
62
. The source/drain regions
12
are each connected via a contact plug
521
to a wiring layer
621
.
The constructions in cross section taken along line A—A and line B—B in
FIG. 29
are illustrated in FIG.
30
and
FIG. 31
, respectively.
As shown in
FIGS. 30 and 31
, the MOS transistors M
1
and M
2
are electrically isolated from each other by a trench isolation oxide film
20
formed in the surface of a semiconductor substrate
1
.
In the MOS transistors M
1
and M
2
, a gate oxide film
30
underlies the gate electrodes
31
and
32
. The gate electrodes
31
and
32
are comprised of a polycrystalline silicon (doped polysilicon) which, for example, contains phosphorus of about 1×10
20
to 5×10
20
/cm
3
as impurity.
In
FIGS. 30 and 31
, the MOS transistors M
1
and M
2
are covered with an interlayer insulating film
40
. The contact plugs
51
,
52
,
511
and
521
are disposed so as to extend through the interlayer insulating film
40
, and the wiring layers
61
,
62
,
611
and
621
are disposed on the interlayer insulating film
40
. Further, an interlayer insulating film (not shown) is disposed on the interlayer insulating film
40
and a wiring layer (not shown) is disposed on this interlayer insulating film. Thus, the wiring layers
61
,
62
,
611
and
621
are electrically connected to this wiring layer.
A method for manufacturing the semiconductor device
80
will be described by referring to
FIGS. 32
to
38
illustrating a sequence of steps in the method.
FIGS. 32
to
38
are cross sections taken along line A—A in FIG.
29
.
In the step of
FIG. 32
, a silicon oxide film
3
and silicon nitride film
4
are formed on the entire surface of the semiconductor substrate
1
. Then, by using a resist mask (not shown), the part of the silicon nitride film
4
and silicon oxide film
3
which corresponds to the region for forming an element isolation oxide film is selectively removed by anisotropic etching.
After the resist mask is removed, trenches
2
are formed by anisotropic etching by using the silicon nitride film
4
as a mask. This results in the construction of FIG.
32
.
In the step of
FIG. 33
, damage by etching is recovered while the inner wall of the trenches
2
is covered with a silicon oxide film
10
by means of thermal oxidation.
In the step of
FIG. 34
, by CVD (chemical vapor deposition) method, a silicon oxide film
201
is formed on the entire surface so as to fill the trenches
2
. Since the silicon oxide film
201
is formed so as to cover the silicon nitride film
4
, the silicon oxide film
201
is left only in the trenches
2
and inside of the opening comprised of the silicon nitride film
4
, by performing planarization with CMP (chemical mechanical polishing) process using the silicon nitride film
4
as a stopper.
In the step of
FIG. 35
, the silicon nitride film
4
and the underlying silicon oxide film
3
are removed to complete a trench isolation oxide film
20
.
In the step of
FIG. 36
, a silicon oxide film is formed on the entire surface by thermal oxidation. Then, for instance, a polycrystalline silicon layer containing phosphorous is deposited on the enter surface by CVD method, and the polycrystalline silicon layer and silicon oxide film are patterned to form gate electrodes
31
and
32
and a gate oxide film
30
. Subsequently, by ion implantation, impurity ion is implanted into the semiconductor substrate
1
such that source/drain regions (not shown) are formed in a self-aligned manner.
If required, the source/drain regions may be of LDD (lightly doped drain) structure by forming a side wall (not shown) and implanting additional impurity ion by ion implantation.
In the step of
FIG. 37
, a silicon oxide film is deposited on the entire surface thereby to form an interlayer insulating film
40
. By using a resist mask (not shown), contact holes extending through the interlayer insulating film
40
to the gate electrode
31
or
32
are opened and the contact holes are then filled with a conductor layer, resulting in contact plugs
51
and
52
.
FIG. 38
is a cross section taken along line B—B of
FIG. 29
, and illustrates the state that contact plugs
511
and
521
reaching the semiconductor substrate
1
are formed.
FIG. 39
illustrates, in plan view, the construction after passing through the steps of
FIGS. 37 and 38
.
Subsequently, a metal layer is deposited on the entire surface of the interlayer insulating film
40
and then patterned to form wiring layers
61
,
62
,
611
and
621
, thereby obtaining the construction shown in
FIGS. 30 and 31
. In addition, an interlayer insulating film (not shown) is formed on the interlayer insulating film
40
and a wiring layer (not shown) is disposed on this interlayer insulating film. Thus, the wiring layers
61
,
62
,
611
and
621
are electrically connected to this wiring layer. Such illustration and description are omitted here.
The foregoing conventional semiconductor device
80
having the MOS transistors is constructed so that the main current passes through a channel formed in the surface of the semiconductor substrate
1
underlying the gate electrodes
31
and
32
, and then f
Horita Katsuyuki
Kuroi Takashi
Okumura Yoshinori
Huynh Andy
Mitsubishi Denki & Kabushiki Kaisha
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