SOI DRAM having P-doped polysilicon gate for a memory pass...

Details SOI DRAM having P-doped polysilicon gate for a memory pass... SOI DRAM having P-doped polysilicon gate for a memory pass...

1997-05-23

2002-07-23

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S350000

Reexamination Certificate

active

06424016

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a the design of DRAMs using Silicon on Insulator (SOI) technology and more particularly to the design of fully depleted memory pass transistors in the DRAM in combination with a P-doped polysilicon gate.
2. Description of the Prior Art
SOI is good for DRAM for several reasons. One reason is that SOI has lower collection volume for charge generated by an alpha particle or a cosmic ray. Such charge can upset the memory cell, so the smaller collection volume of SOI is desirable. SOI also reduces the capacitance on the bit line so less charge is needed to generate an equivalent signal on the bit line relative to bulk DRAM. Also reduced junction area in the memory cell should give lower leakage which translates to longer retention time. All these features, lower collection volume, lower leakage and lower capacitance, are advantages of SOI.
There are also potential difficulties in using SOI for DRAM. These include cost, yield, and floating body effects. SOI wafers cost more than bulk silicon wafers, so it is important to keep the SOI processing cost low. Yield on SOI wafers is expected to improve as the material quality continues to be improved. Floating body effects can improve performance for logic circuits, but can also amplify collected charge (as from alpha particle strikes) or increase leakage currents. So there is a need for a low cost SOI process with reduced floating body effects.
The basic memory cell in a DRAM is a pass and a storage element (capacitor). The full DRAM includes an array of memory cells, and peripheral circuitry to control storage and retrieval of data into and from the memory array. The DRAM may be included with other circuitry in an integrated circuit. The process for a DRAM must encompass the requirements for the memory array pass gate and the peripheral transistors. The requirements for the pass gate transistor distinguish the design of transistors for DRAMs from logic or SRAMs. The pass gate must have very low leakage. This requires relatively high threshold voltage. It is also desirable for the pass gate transistor to have low source capacitance to help keep the bit line capacitance low. For charge transfer, it is usual to have a boosted word line voltage, which leads to thicker gate oxide for reliability. The pass gate transistor does not need to have high drive current. The pass gate transistor is usually N channel with an N doped polysilicon gate. There are some advantages to N polysilicon and the N channel has higher drive because of the higher mobility of electrons.
Peripheral transistors have requirements similar to standard logic transistors. They generally will be designed with lower V
T
than the pass transistor.
But to reduce cost, it is usual to have the peripheral transistor with the same gate oxide and single N polysilicon that is used for the pass transistor. Also, silicide is not used to reduce cost.
Thus the design requirements for the peripheral transistor of a DRAM also may be different from the usual design requirements for standard logic. Nevertheless, we will sometimes refer to the DRAM peripheral transistors as logic transistors.
There are different types of SOI transistors, and the choice of the SOI transistor type will affect the SOI DRAM performance. SOI transistors can be classified as fully depleted or partially depleted. Some SOI transistors may also be classified as nearly fully depleted. These are filly depleted when on and partially depleted when off. For a given channel doping, SOI transistors go from partially depleted to fully depleted as the silicon film thickness is thinned. The partially depleted transistor characteristics, including determination of threshold voltage, are very much like bulk transistors except for the floating body effects. Fully depleted transistors have some unique characteristics, and have reduced floating body effects. For filly depleted transistors, the range of threshold voltage is limited by the gate work function and silicon film thickness. As the channel doping is increased to increase the threshold voltage, the transistor transitions from fully depleted to partially depleted. There is an upper limit of threshold voltage for fully depleted SOI transistors for a given silicon film thickness and gate work function. For logic, it has been proposed to use a mid band-gap work function to raise the threshold voltage of both n and p-channel transistors. Polysilicon gate with “opposite” doping (p type for n-channel and n type for p-channel) has also been proposed combined with accumulation transistor mode design to get suitable threshold voltages for logic or SRAM circuits.
In addition to the difficulty of selecting desirable threshold voltage, fully depleted transistors suffer from higher source/drain resistance because of the thinner silicon film. This is particularly true when silicide is used since there is high contact resistance if the silicide consumes the fill silicon film thickness. For these reasons most commercial work on SOI, including work on SOI DRAM, has emphasized partially depleted transistors.(See H. S. Kim et al. 1995 Synmposium on VLSI Technology Digest of Technical Papers pp. 143, 1995)
For SOI DRAM, the thinner silicon film associated with fully depleted or near fully depleted transistors has several advantages. These include a smaller junction area leading to smaller junction leakage and smaller junction capacitance. The thinner silicon film also provides a smaller volume for charge generation from ion strikes. The fully depleted transistor also has reduced floating body effects that can increase leakage in pass transistors and lead to variation of threshold voltages which would be deleterious to sense amplifiers. Further, the higher series resistance of filly depleted transistors is not significant in the DRAM array, especially since silicide is generally not used. However, the threshold voltage of a fully depleted n-channel SOI transistor with n-poly gate is too low for DRAM pass transistor application.
SUMMARY OF THE INVENTION
It is therefore a general object of the present invention to design an SOI pass transistor for a DRAM that has a high threshold voltage and reduced floating body effects.
It is a further object of the present invention to integrate the above DRAM pass gate transistor with peripheral transistors with suitable characteristics.
These and other objects of the invention will become apparent to those of ordinary skill in the art having reference to the following specification, in conjunction with the drawings.
In this invention, the gate material is chosen to have a higher work function to increase the threshold voltage of the DRAM array pass transistor relative to the use of n-poly for n-channel transistors. This reduces the floating body induced leakage under dynamic conditions. This also allows the use of fully depleted or nearly fully depleted transistors in the array. These can be combined with fully depleted transistors in the periphery. Alternatively, a different thickness silicon film can be used in the array verses in the periphery, such as by selective thinning, to allow fully depleted transistors in the array and partially depleted transistor in the periphery. The use of SOI transistors in the array and bulk transistors in the periphery is also possible.
In a preferred embodiment the pass transistors are fully depleted P channel transistors operating in the inversion mode with N type polysilicon gates. The periphery has fully depleted P channel accumulation mode transistors with N doped polysilicon gates and fully depleted N channel inversion mode transistors also with N type polysilicon gates.
In another embodiment, the pass transistors are fully depleted N channel inversion mode transistors with P type polysilicon gates, wherein the periphery transistors are fully depleted N channel accumulation mode transistors with P type polysilicon gates in addition to filly depleted P channel inversion mode transistors also with P type polysilicon gates.
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