Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-10
2002-08-06
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S903000
Reexamination Certificate
active
06429495
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and more specifically to an address programming device for redundancy decision for semiconductor devices.
2. Description of the Background Art
Conventionally semiconductor memory devices such as SRAM and DRAM are provided with a redundant circuit to improve the yield in manufacturing the semiconductor devices. If a semiconductor memory device manufactured has a defect, the semiconductor memory device is rescued by the function of the redundant circuit. In other words, a row or column of conventional semiconductor memory devices that has a defective memory cell is functionally replaced with a predetermined spare row or column. Thus semiconductor memory devices are provided with a spare memory cell and an address programming circuit for programming a defective address indicative of a location at which a defect is present.
FIG. 20
shows a conventional redundancy decision circuit. In
FIG. 20
, a precharging circuit
120
precharges a common node
121
which receives a complementary address signal. A series circuit formed of a fuse
110
and an n-channel MOS transistor
100
to a series circuit formed of a fuse
118
and an n-channel MOS transistor
108
are connected in parallel between common node
121
and a ground. The gate of each of n-channel MOS transistors
100
to
108
receives an address signal.
In such a redundancy decision circuit, laser is used to blow any of fuses
110
to
118
to program a defective address. If the fuse is not blown, the corresponding address signal is input, the corresponding n-channel MOS transistor is turned on, a precharged voltage of common node
121
is discharged and the potential of common node
121
decreases. However, if the fuse is blown, the precharged voltage of common node
121
is not discharged, even with the corresponding n-channel MOS transistor turned on.
FIGS. 21A-21G
are timing charts for representing an operation of the address programming circuit shown in FIG.
20
.
In the clock cycle represented in
FIG. 21A
, when a bank activating signal represented in
FIG. 21B
attains a high level in response to a command signal, a bank flag represented in
FIG. 21C
attains a high level and a precharge signal /PC is temporarily placed in an off state and common node
121
thus attains a high level. When a complementary address matches a programmed address in this state, the potential of a comparison result MISS represented in
FIG. 21E
does not change and a word line SWL of a spare memory cell represented in
FIG. 21G
is activated. However, if the input complementary address does not match the programmed address, the potential of comparison result MISS changes and a word line MWL for a normal memory cell represented in
FIG. 21F
is activated.
However, the programming by blowing such fuses
110
to
118
shown in
FIG. 20
requires a laser device for blowing the fuses and thus disadvantageously requires extra investment therefor.
SUMMARY OF THE INVENTION
Therefore a main object of the present invention is to provide a semiconductor device optimal for forming a semiconductor device.
Briefly speaking of the present invention, two types of gate oxide films different in thickness are formed on a semiconductor substrate, a gate electrode is formed on the gate oxide films, and the two types of gate oxide films overlap.
Thus, according to the present invention, a semiconductor device optimal for forming a programming device can be formed.
In a preferred embodiment of the present invention, the two types of gate oxide films different in thickness include a gate oxide film serving as an upper layer and a gate oxide film serving as a lower layer, the gate electrode includes gate electrodes respectively formed on the upper and lower gate oxide films, and the gate structure formed by the upper gate oxide film and gate electrode overlaps with the gate structure formed by the lower gate oxide film and gate electrode.
In a still preferable embodiment of the present invention, the semiconductor device configures a programming device. More preferably, the programming device can be formed by forming the lower gate structure as a transistor of a floating structure the threshold value of which can be changed to provide programming. The programming device is employed as a portion of a latch circuit in which an inverted version of program data is written and programmed.
In an aspect of the present invention, a gate electrode is formed on a gate oxide film to provide an upper gate structure and a gate oxide film is formed at a portion underlying the gate structure.
Still preferably, the semiconductor device forms a programming device which is programmed by destroying the gate oxide film formed at the underlying portion. The programming device is employed as a portion of a latch circuit in which an inverted version of program data is written and programmed.
In another aspect of the present invention, an address programming device is formed by a transistor formed by a first, thick gate oxide film formed on a semiconductor substrate, a second, thin gate oxide film formed on the first, thick gate oxide film and a gate electrode formed on the second, thin gate oxide film, wherein a portion of the first, thick gate oxide film is removed and the second, thin gate oxide film is formed thereon.
Still preferably, electric field is applied between the channel region and gate electrode of the transistor, for the programming. Such transistors are arranged in an array.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4132904 (1979-01-01), Harari
patent: 5291435 (1994-03-01), Yu
patent: 5317179 (1994-05-01), Chen et al.
patent: 5631862 (1997-05-01), Cutter et al.
patent: 5652448 (1997-07-01), Chang et al.
patent: 5703388 (1997-07-01), Wang et al.
patent: 5741737 (1998-04-01), Kachelmeier
patent: 5821581 (1998-10-01), Kaya et al.
patent: 5955746 (1999-09-01), Kim
Ooishi Tsukasa
Shimano Hiroki
Tomishima Shigeki
Cao Phat X.
Mitsubishi Denki & Kabushiki Kaisha
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