Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2000-10-26

2002-06-11

Le, Don Phu (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S083000, C327S534000

Reexamination Certificate

active

06404232

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with both a high speed and a low power consumption.
FIG. 2
shows the prior art disclosed by JP-A-8-274620. (Hereinafter, this prior art will be denoted by the prior art A.)
An oscillation circuit OSC
0
is constructed such that an oscillation frequency thereof changes in accordance with the value of a control signal received at a terminal B
1
from a control circuit CNT
0
. The control circuit CNT
0
is constructed such that it receives a reference clock signal CLK
0
from the exterior and receives an oscillation output of the oscillation circuit OSC
0
. A closed circuit system composed of the frequency-variable oscillation circuit OSC
0
and the control circuit CNT
0
inputted with an output S
0
of the frequency-variable oscillation circuit OSC
0
is constructed to form a stable system in which each circuit is applied with a negative feedback. With this closed circuit system, the oscillation frequency of the output S
0
of the frequency-variable oscillation circuit OSC
0
assumes a frequency corresponding to the frequency of the reference clock signal CLK
0
. For example, the oscillation frequency of the output S
0
is synchronous with or the same as the frequency of the external clock signal.
The oscillation circuit OSC
0
is composed of an N-type MOSFET (NMOSFET) and a P-type MOSFET (PMOSFET) formed on a semiconductor substrate and a control voltage from the control circuit CNT
0
changes the substrate bias of the MOSFET. With this construction, the threshold value of the MOSFET changes in accordance with the change in substrate bias so that the oscillation frequency of the oscillation circuit OSC
0
changes.
Further, it is constructed that a main circuit LOG
0
receives a control signal from the control circuit CNT
0
at a terminal B
0
and the control signal controls the substrate biases of MOSFET's forming the main circuit LOG
0
, thereby controlling the threshold voltage of the MOSFET.
With such a construction, it becomes possible to control the threshold voltage of the MOSFET in the main circuit LOG
0
by the reference clock signal CLK
0
so that the threshold voltage of the MOSFET forming the main circuit LOG
0
and hence a power consumption and an operating speed are made variable in accordance with the frequency of the reference clock signal (or in accordance with an operating frequency).
In the prior art A, no limitation is imposed as to a method for distribution of the signal B
0
to the MOSFET's in the main circuit LOG
0
. However, the method for distribution of the substrate bias to the main circuit has a large relation with the power consumption and the packaging density of the main circuit.
In the prior art A, the main circuit LOG
0
is controlled by a signal at B
0
corresponding to a signal at the terminal B
1
. This correspondence has a large relation with the stability of the substrate bias control circuit and the stability of the substrate bias voltage.
In order to solve the two problems mentioned above,
(1) the main circuit LOG
0
in the prior art A is divided into a plurality of substrate control blocks by use of PMOS substrate bias switches and NMOS substrate bias switches, thereby making it possible to control the substrate bias of each circuit block independently of the substrate bias control circuit.
(2) In the embodiment of the prior art A, the signal B
0
inputted to the main circuit LOG
0
is a signal corresponding to the signal B
1
inputted to the frequency-variable oscillation circuit OSC
0
. In an embodiment of the present invention, a substrate bias corresponding to the signal B
0
is particularly generated by use of a substrate bias buffer from a substrate bias corresponding to the signal B
1
. An input impedance of the substrate bias buffer is made high and an output impedance thereof is made lower than the input impedance.
Next, description will be made of a cell layout suitable for construction of a semiconductor device provided with both a high speed and a low power consumption. The present invention relates to a semiconductor device and a cell library or a semiconductor device using the cell library, and more particularly to a semiconductor device in which a substrate bias and a supply voltage can be controlled independently of each other.
The layout of the conventional CMOS inverter is shown in FIG.
13
. Symbol MP
1
denotes a P-type MOS transistor (hereinafter referred to PMOS) composed of P-type diffused (or impurity) layers forming the source and drain of PMOS and a gate electrode, and symbol MN
1
denotes an N-type MOS transistor (hereinafter referred to NMOS) composed of N-type diffusion (or impurity) layers forming the source and drain of NMOS and a gate electrode. Numeral
110
denotes a second metal layer which is supplied with a positive supply voltage (hereinafter referred to as VDD). Numeral
111
denotes a second metal layer which is supplied with a negative supply voltage (hereinafter referred to as VSS).
The substrate or well potential of the PMOS MP
1
(hereinafter referred to as PMOS substrate or well bias) is supplied from a surface high-concentration N layer (hereinafter referred to as PMOS substrate or well diffused (or impurity) layer)
204
. The PMOS substrate or well bias is connected to the second metal layer through a first metal layer
110
so that it is supplied with VDD. The substrate or well potential of the NMOS MN
1
is supplied from a surface high-concentration P layer (hereinafter referred to as NMOS substrate or well diffused (or impurity) layer)
203
. The NMOS substrate or well bias is connected to the second metal layer
111
through the first metal layer so that it is supplied with VSS. Thus, in the prior art shown in
FIG. 13
, the PMOS substrate or well bias is connected to VDD and the NMOS substrate or well bias is connected to VSS.
There is conventionally known a method in which a substrate or well bias is set to a potential different from a supply voltage in order to control the threshold value of a MOS transistor. In the cell structure shown in
FIG. 13
, however, it is not possible to set the substrate or well bias to a potential different from the supply voltage.
FIG. 14
shows the layout of a CMOS inverter cell in the case where it is constructed such that the substrate or well bias of a PMOS and the substrate or well bias of an NMOS can be set to a potential other than VDD and a potential other than VSS, respectively. The substrate or well bias of the PMOS is supplied from a second metal layer
112
, and the substrate or well bias of the NMOS is supplied from a second metal layer
113
. Since the second metal layers
112
and
113
are electrically isolated from second metal layers
110
and
111
, respectively, the substrate or well bias of the PMOS and the substrate or well bias of the NMOS can be supplied with independent potentials.
Circuit diagrams corresponding to
FIGS. 13 and 14
are shown in
FIGS. 15A and 15B
, respectively.
In the case where it is constructed such that the substrate or well bias of the PMOS and the substrate or well bias of the NMOS can be set to a potential other than VDD and a potential other than VSS, respectively, the following is apparent from the comparison of
FIGS. 13 and 14
.
(1) In the case where the height of a cell
300
is made the same as the height of a cell
200
, the width of each of the power supply metal layers
110
and
111
becomes narrow. Thereby, a power supplying capability is deteriorated. (Hereinafter, this will be referred to as a first problem.)
(2) In the case where the power supply metal layers
110
and
111
of the cell
200
are made the same in width as the power supply metal layers
110
and
111
of the cell
200
, the height of the cell
300
becomes higher than the height of the cell
200
because there is a wiring area for the second metal layers
112
and
113
. Thereby, the area is increased. (Hereinafter, this will be referred to as a second problem.)
(3

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2892803