Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-13
2002-09-17
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S288000, C257S327000, C257S328000, C257S329000, C257S335000, C257S339000
Reexamination Certificate
active
06452222
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a MIS (i.e., Metal Insulator Semiconductor) type semiconductor device and a method for manufacturing the same, and more particularly to a horizontal type DMISFET (i.e., Double-diffused MIS Field Effect Transistor) and a method for manufacturing the same.
2. Description of the Related Art
Heretofore, DMOSFETs (i.e., Double-diffused Metal Oxide Semiconductor Field Effect Transistors) have been known as semiconductor power devices for controlling both a relatively large current and a relatively large voltage. Of these DMOSFETs, a horizontal type DMOSFET has its drain electrode disposed in its surface. According to principles of the FET, the horizontal type DMOSFET uses either electrons or electric holes as its majority carriers in operation, and is therefore free from any stored carrier effect. Due to this freedom, the horizontal type DMOSFET is excellent in switching characteristic and in punch-through resistance. Consequently, the horizontal type DMOSFET has widely been used in inductive loads, for example such as switching regulators and the like instruments.
FIG. 15
shows a plan view of a conventional horizontal MIS type semiconductor device.
FIG. 16
shows a cross-sectional view of the conventional horizontal MIS type semiconductor device shown in FIG.
15
. Incidentally, the cross-sectional view shown in
FIG. 16
is taken along a center line L through which a center of a drain region is connected with a center of a base region in the conventional MIS type semiconductor device. Hereinbelow, the conventional horizontal MIS type semiconductor device will be described.
As shown in
FIG. 16
, the conventional horizontal MIS type semiconductor device, more particularly, conventional DMOSFET uses a P
+
-type silicon substrate
51
in which a P
−
-type region
52
for example is previously formed by a suitable crystal growth process such as epitaxial growth processes. Selectively formed in this P
−
-type region
52
is an N-type well region
53
. Selectively formed in a major surface of the thus formed N-type well region
53
is a first P-type base region
54
. Selectively formed in this first P-type base region
54
is a P
+
-type base region
55
. On the other hand, selectively formed in the N-type well region
53
is an N
+
-type drain region
56
. Further, selectively formed in the first P-type base region
54
is an annular P
+
-type source region
57
which is disposed adjacent to a peripheral portion of the P
+
-type base region
55
. This annular P
+
-type source region
57
is oppositely disposed from the N
+
-type drain region
56
. A gate electrode
59
is formed on a gate oxide (i.e., insulation) film
58
which is formed between the annular P
+
-type source region
57
and the N
+
-type drain region
56
. Incidentally, in
FIG. 15
, the reference numeral
60
denotes an element isolation insulation film.
A first interlayer insulation film
61
is formed to cover the entire surface of the semiconductor device including the gate electrode
56
. As is clear from
FIG. 16
, a first contact window
62
is formed on the N
+
-type drain region
56
of this first interlayer insulation film
61
. Through the first contact window
62
, a first layer drain electrode
63
extends upward. On the other hand, a second contact window
64
is formed on both the P
+
-type base region
55
and the annular P
+
-type source region
57
. Through the second contact window
64
, a source electrode
65
extends upward, as shown in
FIG. 16. A
second interlayer insulation film
66
is formed to cover the entire surface of the semiconductor device including both the first layer drain electrode
63
and the source electrode
65
. A third contact window
67
is formed on the first layer drain electrode
63
in the second interlayer insulation film
66
. Through the third contact window
67
, a second layer drain electrode
68
extends upward. The first layer drain electrode
63
is combined with the second layer drain electrode
68
to form a drain electrode assembly. The thus formed semiconductor device has its surface covered with a cover insulation film
69
. In this conventional horizontal MIS type semiconductor device, as is clear from
FIG. 15
, the first P-type base region
54
assumes an octagonal-shaped configuration in plan view to improve the semiconductor device in integration density (i.e., cell density per unit area).
However, the conventional horizontal type DMOSFET has the disadvantage that: when an over-voltage such as surge voltages and counter electromotive forces caused when the DMOSFET connected with an inductive load is turned off is applied to a drain electrode of the DMOSFET, both the displacement current and the breakdown current are forced to flow, so that the DMOSFET is impaired in its endurance of high potential (i.e., over-voltage) failure. In other words, the displacement current concentrates in an area situated on a center line L (shown in
FIG. 15
) along which is defined the shortest distance between the N
+
-type drain region
56
and the annular P
+
-type source region
57
which is oppositely disposed from the N
+
-type drain region
56
. Concentration of the displacement current in the above area is due to the fact that the area in the above-mentioned shortest distance is lowest in resistance to the displacement current. On the other hand, the breakdown current concentrates in each of the corner portions of the polygonal-shaped first P-type base region
54
since the electric field strength is large in each of these corner portions of the first base region
54
.
When both the displacement current and the breakdown current flow in a manner described above, a PN junction formed between the base and the emitter (i.e., between the first base region
54
and the annular P
+
-type source region
57
) of a parasitic NPN transistor (which is constructed of: the N-type well region
53
serving as a collector; the P-type first base region
54
serving as a base; and, the annular P
+
-type source region
57
serving as an emitter) is forward-biased, which facilitates the turn-on action of the above-mentioned parasitic NPN transistor. As a result, current concentration is induced, which leads to a high potential failure of the conventional horizontal type DMOSFET. Due to this, the conventional horizontal type DMOSFET is poor in its endurance of high potential failure.
Another conventional horizontal type DMOSFET improved in its endurance of an over-voltage applied to its drain electrode is disclosed, for example, in Japanese Patent Laid-Open No. Hei9-139438 in which: a deep P-type base region is formed in a first P-type base region in a manner such that the deep P-type base region is larger in depth than the first P-type base portion to decrease in base resistance a parasitic NPN transistor of the DMOSFET, which makes it hard to turn on the parasitic NPN transistor so that an object of the conventional DMOSFET disclosed in the Japanese Patent Laid-Open No. Hei9-139438 is accomplished.
Another conventional but vertical type DMOSFET improved in its endurance of an over-voltage applied to its drain electrode is disclosed, for example, in Japanese Patent Laid-Open No. Hei6-97448 in which: a corner portion of a P-type base region is made free from any formation of an N
+
-type source region; and, an h
FE
(i.e., common-emitter static forward current transfer ratio) in the corner portion of the P-type base region is lowered together with the base resistance of a parasitic NPN transistor of the DMOSFET to make it hard to turn on this parasitic NPN transistor.
However, the conventional horizontal type DMOSFET disclosed in the Japanese Patent Laid-Open No. Hei9-139438 has the disadvantage that: since the deep P-type base region is made deeper in depth than the first base region in order to lower the base resistance of the parasitic NPN transistor, the conventional horizontal type DMOSFET inc
Jackson, Jr. Jerome
McGinn & Gibb PLLC
Ortiz Edgardo
LandOfFree
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