Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-09-24
2002-06-18
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06408425
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of designing a circuit with a field effect transistor (FET), and more particularly to a method of designing an FET circuit for operation with a large signal and a method of determining parameters of a model used in such a method of designing an FET circuit.
2. Description of the Prior Art
Generally, a device model of an FET is used for designing a circuit with an FET. Different device models are used depending on whether the circuit with the FET is to operate with a small signal or a large signal. The large signal refers to an input signal having a large amplitude, determined by the impedance of the circuit with the FET. For example, an input voltage with an input power of 20 dBm is a large signal. The small signal refers to an input signal having a small amplitude. For example, an input voltage with an input power of −20 dBm is a small signal.
If a small signal is inputted to the circuit with the FET, then since the amplitude of the input voltage is small and the voltage varies in a very small range, parameters representing the FET can be handled as being constant, and an output current can be approximated as varying according a linear function of the input voltage. Consequently, the FET can be regarded as a linear circuit when it is operated with the small signal.
If a large signal is inputted to the circuit with the FET, then since the amplitude of the input voltage is large, parameters representing the FET depend on the input voltage, and an output current cannot be handled as a linear function of the input voltage. Therefore, the FET can be regarded as a nonlinear circuit when it is operated with the small signal.
As shown in
FIG. 1
, FET
1
has three terminals, i.e., source S, drain D, and gate G. An equivalent circuit of FET
1
can be expressed as a three-terminal circuit as shown in
FIG. 2
of the accompanying drawings, as disclosed in H. Statz et al., IEEE Transaction On Electron Devices, ED-34, pp. 160-169, February 1987. A similar model is also disclosed in W. R. Curtice, IEEE Transaction on Microwave Theory and Techniques, MTT-33, pp. 1383-1394, December 1985.
If a three-terminal FET is expressed as a three-terminal nonlinear FET, then it has up to 32 device parameters, as is the case with the model of H. Statz et al., as shown in Table 1 below.
TABLE 1
Name
Meaning
&bgr;
Transconductance parameter
VTO
Threshold voltage
&agr;
Current saturation parameter
&lgr;
Output conductance parameter
&thgr;
Statz's b parameter
&tgr;
Transit time under gate
VBR
Gate-drain junction reverse bias breakdown
voltage
IS
Gate junction reverse saturation current
N
Gate junction ideality factor
VBI
Built-in gate potential
FC
Coefficient for forward bias depletion
capacitance
RC
Frequency dependent parameter of output
conductance
CRF
Frequency dependent parameter of output
conductance
RD
Drain ohmic resistance
RG
Gate resistance
RS
Source ohmic resistance
RIN
Channel resistance
CGSO
Zero bias gate-source junction capacitance
CGDO
Zero bias gate-drain junction capacitance
&dgr;1
Capacitance saturation transition voltage
parameter
&dgr;2
Capacitance threshold transition voltage
parameter
CDS
Drain-source capacitance
CGS
Gate-source capacitance
CGD
Gate-drain capacitance
KF
Flicker noise coefficient
AF
Flicker noise exponent
TNOM
Nominal ambient temperature at which the model
parameters were derived
XTI
Temperature exponent for saturation current
EG
Energy gap
VTOTC
VTO temperature exponent
BETATCE
Drain current temperature coefficient
FFE
Flicker noise frequency exponent
If an operation status when a large signal is inputted (operation with a large signal) is expressed by an FET circuit using the three-terminal nonlinear FET model by H. Statz et al., then it is necessary to somehow determine the 32 parameters. Heretofore, it has been customary to determine these parameters with a large expenditure of time and labor.
As described above, in the conventional process of designing an FET circuit, it is necessary to determine many parameters, e.g., 32 parameters, in order to express a nonlinear FET model as a three-terminal circuit model.
Therefore, a large expenditure of time and labor is required to design an FET circuit. Furthermore, the parameters thus determined of the nonlinear FET model are often not satisfactory enough to be able to fully express the actual operation of the FET circuit. To avoid such a drawback, many circuit designers develop their own nonlinear FET models.
There is a switch circuit which has a gate bias circuit designed such that a gate terminal can be seen as being open from an FET in a given frequency band, with only a DC bias being applied to the gate terminal. In such a switch circuit, the FET as it is considered in the given frequency band can be treated as a two-terminal model. For example, a circuit shown in
FIG. 3A
has isolation resistor
4
having a sufficiently large resistance and connected to gate G of an FET. If the FET with isolation resistor
4
connected thereto is operated as a switch circuit, then the FET can be treated as a two-terminal model. Since no DC bias is usually applied between the drain and source of the FET, the FET as it operates with a small input signal is represented by a very simple equivalent circuit. For example, when the FET is in an open-channel state, it can be expressed as simple resistor
7
as shown in
FIG. 3B
, and when the FET is in a pinch-off state, it can be expressed as simple capacitance
5
as shown in FIG.
3
C.
A designing process for expressing such a small-signal equivalent circuit with simple resistor
7
and simple capacitance
5
is disclosed in M. J. Schindler et al., IEEE Transaction on Microwave Theory and Techniques, MTT-35, pp. 1486-1493, December 1987.
If a small-signal equivalent circuit is expressed as a simple two-terminal circuit, i.e., a two-terminal model, then the number of device parameters to be determined for such a two-terminal model is not so large as for the three-terminal model described above. Therefore, the time required to determine the device parameters is shorter, and so is the time required for designing a circuit with an FET. However, it has never been attempted to apply a two-terminal model to the designing of a circuit that is intended to be operated with a large signal. Particularly, a two-terminal nonlinear FET model required to design a large-signal circuit has not been available in the past.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of designing a circuit to achieve a high level of calculation accuracy with a relatively small number of parameters for a large-signal circuit.
Another object of the present invention is to provide a method of determining parameters for a two-terminal model to achieve a high level of calculation accuracy with a relatively small number of parameters for a large-signal simulation.
According to an aspect of the present invention, there is provided a method of designing a circuit with an FET (field effect transistor), comprising the steps of expressing the FET with a two-terminal nonlinear circuit model having a source and a drain, such that a gate terminal thereof is open in at least a frequency band used thereby, and calculating behaviors of the circuit in operation with a large signal represented by a large amplitude of an input voltage, based on the two-terminal nonlinear circuit model.
The two-terminal nonlinear circuit model may be a two-terminal circuit model having a current source whose current varies depending on a voltage and a source-drain capacitance connected parallel to the current source. Alternatively, the two-terminal nonlinear circuit model may be a circuit having a current source whose current varies depending on a voltage and a source-drain capacitance connected parallel to the current source when the FET is in a pinch-off state, and a circuit having only the current source when the FET is in an open-channel state.
According to another aspect of the present invention, there is al
Do Tuan
Hutchins, Wheeler & Dittmar
Smith Matthew
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