Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-02-14
2002-03-12
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S408000
Reexamination Certificate
active
06355955
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to a high performance MOSFET with laterally reduced and/or relatively shallow source/drain regions.
2. Description of the Relevant Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline silicon (“polysilicon”) material over a relatively thin gate oxide. The polysilicon material and the gate oxide are then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (“n-channel”) transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET (“p-channel”) transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used.
The operating characteristics of a MOSFET device are a function of the transistor's dimensions. In particular, the drain current (I
ds
) is proportional to the ratio of the transistor's channel width (W) to the transistor's channel length (L) over a wide range of operating conditions. For a given transistor width and a given biasing condition (e.g., V
G
=3V, V
D
=3V, and V
S
=0V), I
ds
is maximized by minimizing the transistor's channel length L. Minimizing channel length also improves the speed of integrated circuits which include a large number of individual transistors, since the larger drain currents characteristic of short channel devices may quickly drive the adjoining transistors into saturation. Minimizing L is, therefore, desirable from a device operation standpoint. In addition, minimizing the transistor length is desirable because a smaller area of silicon is required to manufacture a transistor having a smaller length. By minimizing the area required for a given transistor, the number of transistors available for a given area of silicon increases, and with it, a corresponding increase in the circuit complexity that can be achieved on the given area of silicon. Moreover, smaller transistors result in smaller die sizes. Smaller die sizes are desirable from a manufacturing perspective because they increase the number of devices that can be fabricated on a single silicon wafer and decrease the probability that any individual die is rendered inoperable during the fabrication process by randomly occurring defects that are caused by contaminating particles present in every fabrication facility.
As transistor length decreases below approximately 1.0 &mgr;m, for example, a problem known as short channel effects becomes predominant. Generally speaking, short channel effects impact device operation by, inter alia, reducing device threshold voltages and increasing sub-threshold currents. As transistor length becomes small enough, the depletion regions associated with the junction areas may extend toward one another and substantially occupy the channel area. Hence, some of the channel will be partially depleted without any influence of gate voltage. Even at times when the gate voltage is below the threshold amount, current between the junctions (often referred to as subthreshold current) nonetheless exists for transistors having a relatively short transistor length.
A problem related to short channel effects, and the sub-threshold currents associated therewith, is the problem of hot-carrier effects. Hot carrier effects are a phenomenon by which hot-carriers (i.e., holes and electrons) arrive at or near an electric field gradient. The electric field gradient, often referred to as the maximum electric field (“Em”), occurs near the drain during saturated operation. More specifically, the electric field is predominant at the lateral junction of the drain adjacent to the channel. The electric field at the drain causes primarily electrons in the channel to gain kinetic energy and become “hot”. These hot electrons traveling to the drain lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs, wherein the pairs migrate to and become injected within the gate dielectric near the drain junction. Traps within the gate dielectric generally become electron traps, even if they are partially filled with holes. As a result, there is a net negative charge density in the gate dielectric. The trapped charge accumulates with time, resulting in a positive threshold shift in the NMOS transistor, or a negative threshold shift in a PMOS transistor. It is known that since hot electrons are more mobile than hot holes, hot carrier effects cause a greater threshold skew in NMOS transistors than PMOS transistors. Nonetheless, a PMOS transistor will undergo negative threshold skew if its transistor gate length is less than, e.g., 0.8 &mgr;m.
Unless modifications are made to the process in which relatively small transistors are formed, problems with sub-threshold current and threshold shift resulting from short channel effects and hot carrier effects will remain. To overcome these problems, alternative drain structures such as double-diffused drains (“DDD”) and lightly doped drains (“LDD”) must be used. The purpose of both types of structures is the same: to absorb some of the potential into the drain and thus reduce Em. The popularity of DDD structures has given way to LDD structures, since DDD structures cause unacceptably deep junctions and deleterious junction capacitance.
A conventional LDD structure is one whereby a light concentration of impurity is self-aligned to the edge of the gate conductor. The light impurity concentration is then followed by a heavier impurity concentration which is self-aligned to a spacer formed on the sidewalls of the gate conductor. The purpose of the first implant dose is to produce a lightly doped section of both the source and drain junction areas at the gate edge near the channel. The second implant dose is spaced from the channel a distance dictated by the thickness of the sidewall spacer. Resulting from the first and second implants, an impurity gradient occurs across the junction from the source/drain area of the junction to the LDD area adjacent the channel.
The distance between the source and drain regions of a transistor is often referred to as the physical channel length. However, after implantation of dopant species into the source and drain regions and subsequent diffusion of the dopant species, the actual distance between the source and drain regions become less than the physical channel length, and is often referred to as the effective channel length (“Leff”). In VLSI designs, as the physical channel length becomes small, so too must the Leff. Decreasing the Leff of a transistor generally leads to an increase in short-channel effects in which the transistor's properties, e.g., the transistor threshold voltage, undesirably vary from their design specification. Absent a comparable reduction in the depth of the source and drain junctions, the severity of the short channel effects resulting from a decrease in Leff may be profound. Accordingly, it has become necessary to scale down the vertical dimensions of the source and drain regions (i.e., the depth of the source/drain implant) to ensure proper operation of transistor devices.
The formation of shallow source and drain regions (i.e., junctions) is, however, rather difficult for PMOSFET devices which include boron-implanted junctions. Due to the relatively high diffusivity and channeling of boron atoms, implanted boron can penetrate deeply into the substrate. While using very low implant energies of boron might produce relatively shallow junctions, advances in techn
Fulford H. Jim
Gardner Mark I.
Kadosh Daniel
Advanced Micro Devices , Inc.
Conley & Rose & Tayon P.C.
Crane Sara
Daffer Kevin L.
Tran Thien F
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