Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
1999-04-06
2002-08-13
Thai, Xuan M. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C710S300000, C710S305000, C710S316000, C326S101000
Reexamination Certificate
active
06434646
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a signal distribution system and method based on a bus arrangement and, more particularly, to a signal distribution system and method based on a bus arrangement comprising an address bus, a data bus, a control bus, and the like.
Conventionally, there are devices called system LSIs (Large Scale Integrated Circuits) in which not only a CPU but also interfaces of memory devices such as a DRAM (Dynamic Random Access Memory) and a ROM (Read Only Memory) and functional units such as an MPEG (Moving Picture image coding Experts Group) decoder are integrated on one chip. In such a system LSI, the functional blocks including a CPU are connected through an address bus, a data bus, a control bus, and the like. The buses are driven and controlled by a bus control circuit formed on the same chip.
FIG. 12
shows a bus arrangement in a conventional system LSI.
As shown in
FIG. 12
, a plurality of functional blocks A to F are arranged on a chip in accordance with their functions. In this case, the block A is a CPU
1
, the block B is a debug unit
2
, the block C is an MPEG decoder
3
, the block D is another functional unit
4
such as a graphic engine, the block E is a DRAM interface
5
, and the block F is a ROM interface
6
. In addition to the functional blocks A to F, a bus signal distribution block
7
and a bus control circuit
8
are integrated on the same chip.
With this arrangement, various bus signals such as an address signal, a data signal, and a control signal output from the functional blocks A to F are temporarily collected by the bus signal distribution block
7
and then distributed to the desired functional blocks A to F through common buses such as an address bus
10
, a data bus
11
, and a control bus
12
. Distribution of bus signals is controlled by the bus control circuit
8
.
Details of the arrangement of the bus signal distribution block
7
will be described.
The bus signal distribution block
7
has a plurality of distribution blocks in correspondence with the types of connected buses. In this case, the bus signal distribution block
7
has an address signal distribution block
71
, a data signal distribution block
72
, a control signal distribution block
73
, an address valid signal distribution block
74
, a read/write signal distribution block
75
, and an address ready signal distribution block
76
.
The input sides of these distribution blocks
71
to
76
are connected to the plurality of buses from the functional blocks A to F, and the output sides are A connected to the common buses such as the address bus
10
, data bus
11
, and control bus
12
. Although not illustrated, bus connection to the address valid signal distribution block
74
and read/write signal distribution block
75
has the same arrangement as that of bus connection to the address signal distribution block
71
, and bus connection to the address ready signal distribution block
76
has the same arrangement as that of bus connection to the control signal distribution block
73
.
Signals output from the distribution blocks
71
to
76
are transmitted to the desired functional blocks A to F through the common buses.
Signal transmission/reception by the functional blocks A to F is performed in the following way.
Address signals output from the functional blocks A, B, C, and D are input to the address signal distribution block
71
. After this, one of the signals is selected under the control of the bus control circuit
8
. The selected address signal is input to one of the functional blocks A to F, which corresponds to the address. At this time, the address signal distribution block
71
drives the entire address bus
10
commonly connected to the functional blocks B to F to input the signal to a desired functional block, as shown in FIG.
13
.
Data signals output from the functional blocks A to F are input to the data signal distribution block
72
, and then, one of the signals is selected under the control of the bus control circuit
8
. The selected data signal is input to one of the functional blocks A to F, which is designated by an address signal in advance. At this time, the data signal distribution block
72
drives the entire data bus
11
commonly connected to the functional blocks A to F to input the signal to a desired functional block, as shown in FIG.
14
.
Control signals from the functional blocks B to F are input to the control signal distribution block
73
. After this, one of the signals is selected under the control of the bus control circuit
8
. The selected control signal is input to one of the functional blocks A to F, which is designated by an address signal in advance. At this time, the control signal distribution block
73
drives the entire control bus
12
commonly connected to the functional blocks A to D to input the signal to a desired functional block, as shown in FIG.
15
.
That is, the types of signals input/output to/from the functional blocks A to F are determined in accordance with the functions of the functional blocks A to F. For example, since the functional block A comprises a CPU, an address signal is output, and a data signal is input or output, although no address signal is input.
Since the functional blocks B, C, and D comprise peripheral functional units such as a debug unit and an MPEG decoder, both address signals and data signals are input or output.
The functional blocks E, and F comprises interfaces of memory devices such as a DRAM and a ROM, address signals are input but not output. A data signal is input/output to/from the functional block E to read/write data. However, the functional block F is used to merely read out a data signal, so the data signal is only output.
However, in the above-described prior art, the entire common bus must be driven only to input a signal to one functional block, resulting in an increase in power consumption.
The conventional arrangement still has an advantage that the circuit arrangement is simple because all functional blocks are connected to one common bus. However, along with today's development in micropatterning, wiring can be more easily led, and a demand has arisen more for reduction of power consumption during operation than for a simple circuit arrangement.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a signal distribution system and method based on a bus arrangement for reducing power consumption.
In order to achieve the above object, according to the present invention, there is provided a signal distribution system comprising a plurality of functional blocks divided into a plurality of groups each of which receives bus signals of the same type, at least one bus signal distribution block for distributing a bus signal received from a transmission source functional block to a transmission destination functional block, at least one bus connected between the bus signal distribution block and the functional blocks, the bus having division buses arranged in units of groups of the functional blocks, and bus control means for controlling the bus signal distribution block to select one of the division buses connected to a transmission destination group on the basis of an address signal received from the transmission source functional block and transmit the received bus signal to the transmission destination functional block in the transmission destination group through the selected division bus.
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Japanese Office Action issued Mar. 7, 2000 in a related application with English translation of relevant portions.
Japanese
Dickstein Shapiro Morin & Oshinsky LLP.
NEC Corporation
Thai Xuan M.
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