Static information storage and retrieval – Systems using particular element – Resistive
Reexamination Certificate
2001-08-31
2002-05-07
Phan, Trong (Department: 2818)
Static information storage and retrieval
Systems using particular element
Resistive
C365S158000
Reexamination Certificate
active
06385079
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention pertains to the field of resistive memory cell arrays. More particularly, this invention relates to methods and structure for memory in a resistive memory array for maximizing the signal to noise ratio of the array.
2. Background
A resistive random access memory (RAM) is a cross point type memory array of a planar matrix of spaced memory cells sandwiched between two meshes of conductors running in orthogonal directions above and below the cells. An example is the resistive RAM array
10
shown in FIG.
1
. The row conductors
12
running in one direction are referred to as the word lines, and the column conductors
14
extending in a second direction usually perpendicular to the first direction are referred to as the bit lines. The memory cells
16
are usually arranged in a square or rectangular array so that each memory cell unit
16
is connected with one word line
12
and an intersecting bit line
14
.
In a resistive RAM array, the resistance of each memory cell has more than one state, and the data in the memory cell is a function of the resistive state of the cell. The resistive memory cells may include one or more magnetic layers, a fuse or anti-fuse, or any element that stores or generates information by affecting the magnitude of the nominal resistance of the element. Other types of resistive elements used in a resistive RAM array include poly-silicon resistors as part of a read-only memory, and floating gate transistors as part of optical memory, imaging devices or floating gate memory devices.
One type of resistive random access memory is a magnetic random access memory (MRAM), in which each memory cell is formed of a plurality of magnetic layers separated by insulating layers. One magnetic layer is called a pinned layer, in which the magnetic orientation is fixed so as not to rotate in the presence of an applied magnetic field in the range of interest. Another magnetic layer is referred to as a sense layer, in which the magnetic orientation is variable between a state aligned with the state of the pinned layer and a state in misalignment with the state of the pinned layer. An insulating tunnel barrier layer sandwiches between the magnetic pinned layer and the magnetic sense layer. This insulating tunnel barrier layer allows quantum mechanical tunneling to occur between the sense layer and the pinned layer. The tunneling is electron spin dependent, causing the resistance of the memory cell, a function of the relative orientations of the magnetizations of the sense layer and the pinned layer. The variations in the junction resistance for the two states of the sense layer determine the data stored in the memory cell. U.S. Pat. No. 6,169,686, granted to Brug et al. on Jan. 2, 2001 discloses such a magnetic memory cell memory.
Referring to
FIG. 2
, a MRAM memory cell is shown. Memory unit
16
is shown as a three-layer memory cell
20
. In each cell
20
a bit of information is stored according to the orientation of a magnetic sense layer
22
of the cell
20
. Usually, the cell
20
has two stable magnetic states corresponding to the logic states “1” and “0.” The two-way arrow
15
on the sense layer
22
shows this binary-state capability. A pinned layer
24
in the cell
20
is separated from the sense layer by a thin insulator
26
. Pinned layer
24
has a fixed magnetic orientation, such as shown by the one-way arrow
17
on layer
24
. When the magnetic state of the sense layer
22
is oriented in the same direction as the direction of the magnetization of the pinned layer
24
, the cell magnetization is referred to as “parallel.” Similarly, when the magnetic state of the sense layer
22
is oriented in the direction opposite to the direction of the magnetization of the pinned layer
24
, the cell magnetization is referred to as “anti-parallel.” These orientations correspond to a low resistance state and a high resistance state, respectively.
The magnetic state of a selected memory cell
20
may be changed by applying currents to a word line
12
and a bit line
14
crossing the selected memory cell. The currents produce two orthogonal magnetic fields that, when combined, will switch the magnetic orientation of the selected memory cell
20
between the parallel and anti-parallel states. Other unselected memory cells receive only a magnetic field from either the word line or the bit line crossing the unselected memory cells. The single field is not strong enough to change the magnetic orientation of the unselected cells, so they retain their magnetic orientation.
Referring to
FIG. 3
, an MRAM memory array
30
is shown. A sense amplifier
32
is connected to the bit line
34
of a selected memory cell
36
. A voltage V
r
is applied to the word line
38
of the selected memory cell
36
, and sense amplifier
32
applies a voltage to the bit line
34
of cell
36
. The sense amplifier
32
provides an amplified output
39
reflecting the state of the memory cell
36
. The same bit line voltage is applied to all of the bit line
34
, effectively biasing all the cells on unselected rows to zero potential. This action isolates the bit line currents from one another, effectively blocking most of the leakage current that might otherwise flow through secondary paths, possibly causing errors in the sensing function of the selected memory cell.
It is understood that the conductors of the word lines and bit lines in the magnetic array all have some amount of resistance to the flow of electricity through the lines. Also, a low resistance state and a high resistance state, corresponding to memory states “0” and “1” across the junction of the cross point cell. Although the effects of each such resistance is negligible in itself, the combined effect of these resistances in an array, particularly the conductor resistances, causes some reduction in the available sense current for the sense amplifier to determine the states “0” and “1” of the memory cell. If the array becomes too large, the conductor resistances increase because there are more rows and columns. Thus, more current is flowing, and the leakage current through the “sneak paths” also increases. Larger current and higher row and column conductor resistance in a large array can cause substantial voltage drops along the word lines and an unequal potential in the bit lines. These effects cause significant reduction in the sense current available to the sense amplifier that can lead to errors in sensing the states of the memory cells.
The problem of errors caused by combined resistances of the conductors becomes worse as the number of memory cells in a memory array are increased. Each conductor must be longer to connect to the increased number of memory cells, resulting is greater line resistance for each conductor. In addition, as arrays become larger, the design of the memory array is scaled smaller to increase the capacity without increasing size of the array. The conductors are made correspondingly thinner and narrower to be able to write data to the memory cells without substantially increasing the write current in the row and column conductors. This decreased thickness of the conductor results in more resistance along each conductor, increasing the possibility of errors or “noise” that interferes with the array output or signal.
The “magneto-resistive tunnel junction” (MTJ) junction of each memory cell in a MRAM array can also be a factor. As the memory is scaled down in size in order to increase capacity without substantially increasing the array size, there is an increase in MTJ resistance. This increased resistance leads to less tunneling current through the MTJ, thereby reducing the signal current. A “tunneling current” across the junction of each memory cell is a function of the MTJ resistance of each memory cell and can also contribute to the noise of the array. The MTJ resistance across the junction is affected by the material used in the cell and the respective polarizations of the layers on each side of the junction. See Sharma, et al
Hewlett--Packard Company
Phan Trong
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