Methods of forming portions of transistor structures,...

Details Methods of forming portions of transistor structures,... Methods of forming portions of transistor structures,...

2000-03-03

2002-07-16

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S303000, C257S344000

Reexamination Certificate

active

06420250

ABSTRACT:

TECHNICAL FIELD
The invention pertains to methods of forming transistor structures, as well as to methods of forming array and peripheral circuitry. Also, the invention pertains to structures comprising transistor gates.
BACKGROUND OF THE INVENTION
Transistor gates are commonly utilized as electrical components in semiconductor circuits. The transistor gates comprise electrically conductive materials, and a continuing goal in semiconductor processing is to develop structures for electrically insulating the conductive gate materials relative to surrounding conductive circuitry. Typically, the conductive gate materials have an electrically insulative cap formed on top of them, and also have electrically insulative spacers formed alongside them. Among the challenges in semiconductor processing is a continuing goal to reduce process steps. Accordingly, it is generally desired to incorporate the formation of insulative materials adjacent a conductive gate with other process steps. For instance, the insulative spacers formed alongside a conductive gate are frequently utilized not only for insulating the gate, but also for aligning a subsequent source/drain implant into a substrate adjacent the gate.
It is noted that not only is there a continuing goal to reduce process steps in fabrication of individual gates, but there is also a goal to reduce fabrication steps relative to a plurality of transistors formed on a common semiconductive material wafer. For instance, a memory chip will frequently have an array of transistors utilized in memory devices (a so-called memory array), and other transistors surrounding the array and utilized in logic functions (so-called peripheral circuitry). It is desired to develop fabrication steps which simultaneously form structures in both memory array regions and peripheral circuitry regions of a memory chip.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses a method of forming a portion of a transistor structure. A substrate is provided, and a transistor gate is formed over the substrate. The transistor gate has a sidewall. A silicon oxide is deposited over a portion of the substrate proximate the transistor gate by high density plasma deposition. A spacer is formed over the silicon oxide and along the sidewall of the transistor gate.
In another aspect, the invention encompasses a method of forming memory array and peripheral circuitry. A substrate is provided. A memory array region and peripheral circuitry region are defined within the substrate. A pair of adjacent memory transistor gates are formed over the memory array region of the substrate, and the pair of adjacent peripheral transistor gates are formed over the peripheral region of the substrate. The adjacent peripheral transistor gates are separated by a larger distance than are the adjacent memory transistor gates. A spacer material is formed over the memory transistor gates, as well as over a portion of the substrate between the memory transistor gates. Also, the spacer material is formed over the peripheral transistor gates, as well as over a portion of the substrate between the peripheral transistor gates. The spacer material is etched to form separated spacers between the adjacent peripheral transistor gates, but the etching does not form separated spacers between the adjacent memory transistor gates.
In yet another aspect, the invention encompasses a method of oxidizing a portion of a conductive structure. A conductive structure is formed over a substrate. The conductive structure comprises a conductively-doped semiconductive material and a metal-containing material over the conductively-doped semiconductive material. The structure comprises a sidewall, and the sidewall has a portion defined by the metal-containing material as well as a portion defined by the conductively-doped semiconductive material. A silicon oxide is formed along the sidewall. The silicon oxide is along at least some of the portion defined by the conductively-doped semiconductive material, and is not along the portion defined by the metal-containing material. A silicon nitride is formed over the silicon oxide. The silicon nitride is along the portion defined by the metal-containing material. At least some of the portion of the sidewall defined by the conductively-doped semiconductive material is oxidized through the silicon oxide. The silicon nitride is utilized as a protective barrier over the portion of the sidewall defined by the metal-containing material to protect the metal-containing material from being oxidized during the oxidizing of the portion of the sidewall defined by the conductively-doped semiconductive material.
In other aspects, the invention encompasses transistor gate structures, as well as structures comprising memory array and peripheral circuitry.


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