Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-03-04
2002-05-21
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06393601
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to designing a layout for a semiconductor integrated circuit. More specifically, the present invention relates to technologies for determining an optimum transistor size in designing a layout.
In a conventional method for designing a layout for a semiconductor integrated circuit, first, the size of each of the transistors, constituting the integrated circuit, is determined before the layout designing is started. Thereafter, the arrangement of the transistors and the wiring among the transistors are performed based on the determined transistor size.
In arranging the transistors, a technique called “diffusion sharing”, in which one and the same diffusion region is shared among a plurality of transistors having an equal potential, is generally used in order to reduce the diffusion capacitance between these transistors and to reduce the area occupied by these transistors on a chip. If there is any transistor having a gate, which is larger in size than the arrangement region assigned thereto, then such a transistor is divided into several smaller transistor sections. In such a case, it is also common that one and the same diffusion region is shared among the transistor sections. Such a division of a large-size transistor into smaller transistor sections is called a “transistor folding” technique. In this specification, the smaller transistor sections, which have been divided from one large-size transistor, will be called “transistor folded sections” and the number of such sections will be called a “number of transistor folded sections”.
On the other hand, the methods for determining the transistor size include: a method for determining the size of a transistor based on simple equations by assuming the area and the diffusion capacitance of the transistor to be proportional to the size of the transistor (disclosed by Fishburn et al., in “TILOS: A Posynomial Programming Approach to Transistor Sizing”, ICCAD 85, pp. 326-328, 1985); a method in which the size determination and the compaction of a transistor are repeatedly performed by using the real capacitance (obtained after the layout has been designed) as the diffusion capacitance (disclosed by Yamada et al., in “Synergistic Power/Area Optimization with Transistor Sizing and Wire Length Minimization”, IEICE Trans. Electron., Vol. E78-C, No. 4, pp. 441-446, 1995); and the like.
In accordance with these conventional layout designing methods, however, the number of transistor folded sections cannot be optimized by using, as design indices, the area occupied by the transistors and the resulting circuit characteristics such as the delay performance thereof. Thus, the conventional methods have no choice other than designing a layout by using a non-optimized transistor size and a non-fixed number of transistor folded sections, or re-determining the transistor size after the transistors have been arranged once, in order to optimize the transistor size and the number of folded sections.
Moreover, in the conventional methods for determining a transistor size, the decrease in area and diffusion capacitance of the transistors, resulting from the serial connection, the folding and the like of the transistors, are not taken into consideration. Thus, the transistor size cannot be optimized with high precision. For example, the method of Fishburn et al. can determine a transistor size in a relatively short time. However, since the method of Fishburn et al. does not take the diffusion sharing among the transistors, which is implemented when the transistors are actually laid out, into consideration at all, the transistor size cannot be optimized with high precision. On the other hand, the method of Yamada et al. is a combination of the conventional compaction technique and the method of Fishburn et al., and does take the diffusion sharing into consideration. However, in accordance with the method of Yamada et al., since the size determination and the compaction of a transistor need to be repeated many times, an enormous amount of time is required for processing. Furthermore, the method of Yamada et al. cannot optimize the transistor size and the number of transistor folded sections simultaneously.
SUMMARY OF THE INVENTION
An objective of the present invention is optimizing the size and the number of folded sections of each of the transistors, constituting an integrated circuit, without re-setting the transistor size in designing a layout for the integrated circuit.
Another objective of the present invention is optimizing a transistor size with higher precision and in a shorter time, as compared with a conventional method, in determining the transistor size for designing a layout for an integrated circuit.
Still another objective of the present invention is providing a circuit characteristic evaluating method, which can optimize a transistor size with higher precision and in a shorter time, as compared with a conventional method.
Specifically, the present invention provides a layout designing apparatus for an integrated circuit receiving circuit data representing a configuration of the integrated circuit to be designed and technology data representing information about a semiconductor fabrication process. The layout designing apparatus includes: transistor size determination means for determining a size and a number of folded sections of each of a plurality of transistors, which constitute the integrated circuit, based on the circuit data and the technology data, while evaluating characteristics of the integrated circuit; and layout means for determining an arrangement of the transistors and wiring among the transistors, based on the circuit data, the technology data, the transistor size and the number of folded sections, which size and number have been determined by the transistor size determination means, thereby producing a layout for the integrated circuit.
In the layout designing apparatus for an integrated circuit, before the layout is produced, the transistor size determination means can determine the size and the number of folded sections of each of the transistors, which constitute the integrated circuit to be designed, while evaluating the characteristics of the integrated circuit. Thus, the size and the number of folded sections of each transistor can be optimized without re-determining the transistor size.
In one embodiment of the present invention, the transistor size determination means of the layout designing apparatus for an integrated circuit preferably includes: diffusion sharing estimation means for estimating, based on the circuit data, a diffusion-sharing region where diffusion sharing is implemented in the layout of the integrated circuit, when a given transistor size candidate is employed; circuit characteristic evaluation means for evaluating the characteristics of the integrated circuit when the given transistor size candidate is employed, based on the circuit data, the technology data and information about the diffusion-sharing region estimated by the diffusion sharing estimation means; and transistor size optimization means for setting transistor size candidates of the integrated circuit, in which the given transistor size candidate is included, providing the size candidates to the diffusion sharing estimation means and the circuit characteristic evaluation means, and then selecting an optimum transistor size from the transistor size candidates based on evaluation results of the circuit characteristic evaluation means.
In such a configuration, when a transistor size candidate is given by the transistor size optimization means, the diffusion sharing estimation means estimates the diffusion-sharing region and the circuit characteristic evaluation means evaluates the characteristics of the integrated circuit in consideration of the information about the diffusion-sharing region estimated by the diffusion sharing estimation means. In this manner, by making the transistor size optimization means set various transistor size candidates and select an optimum transistor size
Fukui Masahiro
Tanaka Masakazu
Do Thuan
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Smith Matthew
LandOfFree
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