Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-31
2002-04-16
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S304000
Reexamination Certificate
active
06373087
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of fabricating a capacitor in a semiconductor device and, more particularly, to methods of fabricating a metal-oxide-metal capacitor in a metal-oxide semiconductor device and associated apparatuses.
BACKGROUND OF THE INVENTION
Capacitors are commonly used in electronic devices for storing electrical charge. Typically, a capacitor consists of an insulator or dielectric material sandwiched between parallel conductive plates. When a voltage differential is applied across the plates, a certain electrical charge is stored by the insulator, wherein the amount of electrical charge is known as the capacitance of the capacitor. The capacitance is generally measured in units of farads and corresponds to the amount of charge stored by the capacitor per the applied voltage. The capacitance of the capacitor may be affected by various factors including the surface area of the plates contacting the insulator, the thickness of the insulator (the distance between the plates), and the dielectric constant of the insulator. Although capacitors are commonly used in macroelectronics applications, capacitors may also be used in various microelectronics applications such as in electrical filters, analog-to-digital converters, and other microelectronic devices.
A particular example of a capacitor adapted to microelectronics applications is a metal-oxide-metal (MOM) capacitor, typically used in, for example, analog semiconductor devices and the like. An example of a process for fabricating MOM capacitors is disclosed in, for example, U.S. Pat. No. 5,576,240 to Radosevich et al., assigned to Lucent Technologies Inc., also the assignee of the present invention, and incorporated herein by reference. The Radosevich '240 patent discloses a method of fabricating a metal to metal capacitor which comprises a layer of titanium/titanium nitride deposited on a polysilicon which has been patterned with interlevel dielectrics. A capacitor dielectric is then deposited, followed by the deposition of an aluminum layer. Interspersed between the deposition steps are appropriate patterning and etching steps for defining the capacitor. Such a MOM capacitor exemplifies a relatively inexpensive design that is typically compatible with back-end wiring processes.
However, an ongoing trend in the production of semiconductor devices is the move toward devices with progressively smaller features, wherein a feature may comprise, for example, a capacitor as described herein. Popular techniques for forming metallic features in semiconductor devices involves deposition of a metallic layer over a substrate, followed by subsequent photolithographical patterning and etching steps to produce the desired configuration of the metallic feature as described in, for example, the Radosevich '240 patent. Metals such as aluminum that are typically used for these metallization processes are capable of forming the desired features and are relatively easy to process. However, as the size of a metallic structure decreases, it is often more difficult to obtain the desired configuration of the feature with standard deposition, patterning, and etching techniques. In addition, reduction in the size of metallic features often results in, for example, a detrimental increase in the resistivity of the feature. An increase in the resistivity of the metallic components may, for instance, further lead to a deleterious reduction in the processing speed of the device. Further, a metal such as aluminum may have a relatively low melting point. Thus, after the deposition of an aluminum metallization layer, subsequent processing steps must often be performed at temperatures under a specific limit in order to avoid damage to a previously formed aluminum metallization layer.
One solution to these shortcomings has been to use another metal, such as copper, for certain metallization processes. Copper has a lower resistivity which allows for the formation of smaller features than with aluminum metallization. Copper also has a higher melting point relative to aluminum such that subsequent device processing steps may be performed at higher temperatures. However, the typical deposition, patterning and etch processes are not as effective for copper metallization processes as they are for aluminum metallization processes. Generally, adaptation of these standard processes to copper metallization is relatively difficult and often cost prohibitive. For example, it would not be feasible to simply replace the titanium/titanium nitride layer in the Radosevich '240 device with a copper layer due to, for instance, difficulties associated with the etching of copper. Further, a metal such as copper may have a tendency to diffuse ions of the metal into any surrounding insulating or dielectric structure, thereby leading to leakage or other undesirable results. Thus, there exists a need for a metallization process in the production of metal-oxide semiconductor devices wherein a metal other than aluminum, such as copper, can be relatively easily applied in a cost effective manner to form metallic features in the device while permitting flexibility in the miniaturization of such features.
As with any fabrication process, a simpler process is generally more advantageous. Thus, a fabrication method which can achieve the same or better quality product with about the same material cost and with the same or fewer processing steps is highly preferred, especially if elimination of steps in the fabrication process reduces labor costs and eliminates the need for expensive manufacturing equipment. In addition, it is generally desirable to retain flexibility in the fabrication process for semiconductor devices such as integrated circuits. More particularly, it is advantageous to have a modular process for forming a capacitor wherein the modular capacitor formation process may be added as an option at various stages in the fabrication of the integrated circuit, without major changes in the sequence of the fabrication processes.
Thus, it would be advantageous to have a metallization process in the production of metal-oxide semiconductor devices wherein a metal other than aluminum, such as copper, can be relatively easily applied in a cost effective manner to form metallic features while permitting flexibility in the miniaturization of such features. This process should be simple, modular, and flexible, while producing an improved semiconductor device.
SUMMARY OF THE INVENTION
The above and other needs are met by the present invention which, in one embodiment, provides a method of fabricating a capacitor in a microelectronic device. First, a recess is formed in a surface of a dielectric layer deposited over a microelectronic substrate. A first barrier layer is then deposited over the dielectric layer such that the first barrier layer conforms to the recess. A first conductive element is then deposited over the first barrier layer so as to at least fill the recess. A second barrier layer is then deposited over the first conductive element such that the first barrier layer and the second barrier layer cooperate to encapsulate the first conductive element. The first conductive element thus comprises a first plate of the capacitor. A capacitor dielectric layer is then deposited over the second barrier layer, followed by the deposition of a conductive second conductive element over the capacitor dielectric layer. The second conductive element thus comprises a second plate of the capacitor.
In one advantageous embodiment, the dielectric layer comprises an oxide layer and the microelectronic substrate comprises a silicon substrate, wherein forming a recess thereby further comprises forming an oxide layer on a surface of a silicon substrate. In such an instance, the recess is formed in the oxide layer by an oxide etch process. The first and second barrier layers encapsulating the first conductive element may be comprised of, for example, tantalum; tantalum nitride; titanium nitride; tungsten nitride; silicon nitrides of tantalum, t
Harris Edward Belden
Merchant Sailesh Mansinh
Yan Yifeng Winston
Agere Systems Guardian Corp.
Alston & Bird LLP
Nelms David
Vu David
LandOfFree
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