Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-06-19
2002-03-05
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S108000, C438S127000
Reexamination Certificate
active
06352878
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to flip chip packaging for integrated circuits. More particularly, it relates to flip chips that have an integral layer of underfill material and to methods for and apparatus for packaging such flip chips.
BACKGROUND OF THE INVENTION
There are a number of conventional methods for packaging integrated circuits. One approach, referred to as “flip chip” packaging, generally involves forming solder bumps (or other suitable contacts) directly on I/O pads formed on an integrated circuit die. The die is then typically attached to a substrate such as a printed circuit board or package substrate such that the die contacts directly connect to corresponding contacts on the substrate. That is, the die is placed on the substrate with the contact bumps facing corresponding contacts on the substrate. The solder contact bumps are then reflowed to electrically connect the die to the substrate.
When a flip chip is attached to the substrate, an air gap typically remains between flip chip and substrate. This gap is commonly filled with material that is flowed into the gap in liquid form and is then solidified. This material, a plastic material, is generally called “underfill”. The underfill material is typically applied in liquid form from a dispenser at one edge of a flip chip. The material then flows into the narrow gap and spreads across the flip chip until the entire area of the gap between flip chip and substrate is filled. The underfill process improves reliability of the flip chip interconnect and lowers mechanical stress on the contacts.
There are problems associated with underfill. When the operation of applying underfill is repeated for each flip chip, manufacturing costs are relatively high. To address this issue and to lower manufacturing cost, wafer-level underfill processing is being developed. This process involves encapsulating an entire bumped wafer surface with underfill material prior to singulating the wafer into individual dies and attaching the dies to the board.
A method of encapsulating a bumped wafer surface is described in co-pending application Ser. No. 09/359,074, the specification of which has been incorporated herein by reference, wherein a wafer is paced into a mold with the wafer backside positioned on a bottom plate and a top plate placed atop the bumps, and underfill material is injected between the top plate and the wafer surface. However, encapsulating an entire bumped flip chip wafer presents new challenges.
One problem which arises is the creation of voids in the underfill material caused by air being trapped between the bumps. The typical height of a flip chip bump is 4 to 5 mils, and therefore the gap between the surface of the wafer and the top plate, i.e., the gap to be filled with underfill material, is approximately 4 mils. Typical pitches for the bumps are approximately 10 mils. With wafer diameters as great as 12 inches, it is extremely difficult to inject underfill material and completely fill the gap without voids, using methods currently in the art. Voids in the underfill material can adversely affect the mechanical strength and therefore the reliability of the interconnect. In addition, moisture can become trapped within voids, which when subjected to subsequent surface mount or other high temperature processes can cause corrosion or cracking. Therefore there is a need for improved wafer level underfill processes.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, a method and apparatus for forming a layer of underfill encapsulant on an integrated circuit wafer are disclosed.
In a preferred embodiment, the wafer includes integrated circuits having electrically conductive pads exposed on a surface of the wafer, a plurality of the electrically conductive pads having solder bumps thereon. The wafer is installed into a mold cavity, air is evacuated from the mold cavity, and a layer of underfill encapsulant is formed on the wafer surface while in the evacuated mold cavity. In the preferred embodiment, some of the integrated circuits are flip chip integrated circuits.
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Mostafazadeh Shahram
Smith Joseph O.
Lebentritt Michael S.
National Semiconductor Corporation
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