Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-30
2002-08-06
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S390000, C257S032000, C257S009000
Reexamination Certificate
active
06429494
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a semiconductor read-only memory (ROM) with parallel trenches, with bit lines running along the trench bases and on the trench crowns in a longitudinal direction of the trenches, and word lines running transversely thereto and transistors formed vertically in the trench side-walls. The invention further relates to a method for manufacturing such a semiconductor read-only memory. In such a semiconductor read-only memory, a programming is carried out by a suitable manipulation of the memory transistors during the manufacturing process.
Such ROMs usually have a plurality of parallel bit lines and a plurality of parallel word lines. The bit lines run via the source and drain terminals of the memory transistors.
The word lines run perpendicularly to the bit lines and connect the gate terminals of respective rows of memory transistors to one another. There are natural limits on the miniaturization of such a configuration. The gate of each transistor must have a specific minimum length to ensure that the flow of current between the source and the drain is reliably pinched off when the memory transistor is switched to the blocked state. The minimum distance between gate electrodes is furthermore determined by the manufacturing process.
Various modifications of customary ROMS have been proposed in order to achieve an increased packing density.
German Published, Non-Prosecuted Patent Application DE 42 14 923 A1 discloses a mask ROM device having a NAND structure and a method for manufacturing such a device. A plurality of trenches, which extend parallel to one another, are formed in a memory transistor area on the surface of a silicon substrate. MOS memory transistors use the trench side-walls as channel regions. For this purpose, a thin gate oxide is applied to the side walls and a gate electrode is in turn applied thereon. The bit lines run perpendicularly to the direction of the trenches, on the crowns and on the base alternately. The word lines are provided at a right angle thereto.
The ROM is programmed by doping the channel of selected memory transistors using a suitably masked implantation. As a result, by appropriately selecting the doping materials and their concentration the turn-on voltage of these memory transistors can be increased to a value which is above the operating voltage. Doped memory transistors thus block when the operating voltage is applied during the reading process of the ROM, while non-doped transistors switch through when the operating voltage is applied.
An alternative programming process consists of filling the trenches with an insulator and etching a hole into the insulator at those points on the trench side-wall at which a transistor, which switches through, is to be produced. Then, in a further manufacturing step, a gate oxide is formed on the wall of the hole. Polysilicon is then applied to the gate oxide in order to form the gate electrode. The regions of the trench side-walls in which a gate has not been formed form the cells which block when the operating voltage is applied.
Although the two programming methods described provide usable results, they have a number of specific problems.
In the programming method known from German Published, Non-Prosecuted Patent Application DE 42 14 923 A1, the implantation of the doping, and thus the adjustment of the turn-on voltage takes place with an oblique angle of incidence with respect to the trench side-walls. This oblique doping is also significant for the instant invention. The masking, which is used for the selective implantation is manufactured through the use of photographic patterning and is removed again after the implantation process. It is therefore then no longer possible to discern the position of the implantation. As a result, it is also no longer possible to align the gate oxide and gate electrode layers, which then have to be applied in the following manufacturing steps, directly with the position of the implantations. Accordingly, there is the risk of misalignment, so that the gates are not precisely formed over the implanted regions of the channels. As a result, it is possible for part of the channel of a memory transistor, which should normally be blocked even when the operating voltage is applied, to have sufficiently good conductivity. Undesired leakage currents, which increase the power requirement of the ROM, or even falsify the programming, will then flow. Furthermore, it is not readily possible to integrate this form of programming with a memory manufactured by the use of shallow-trench isolation (STI). The trenches have to be produced in a separate lithography and etching step after the STI process is finished. The gate polysilicon then runs over the topography, making lithography and patterning of the gate level more difficult.
The second-mentioned programming method also has a number of problems. Programming is carried out through the use of a photolithographically patterned resist mask which leaves those regions open at which a hole is to be etched into the insulator. Here too, problems arise as a result of the alignment of the programming mask, which cannot always be maintained precisely. If the trenches have the minimum phototechnically achievable width F, the misalignments of the programming mask in the direction of the word lines leads to a situation in which the overlapping between the trench and opening becomes smaller than the actual cross-section of the hole and in particular may become significantly smaller than F/2. However, on the other hand, holes with the full width (≧F) of the trench will also have to be etched at the points where two transistors should lie opposite one another in a trench. During the following etching process, it is therefore necessary to etch holes which have significantly different cross-sections. Since the customary oxide etching processes open small holes more slowly than large ones, the lower bit line is already severely attacked in the large holes, while the small holes have not yet been correctly opened. The upper bit line is also inevitably overetched unless it can be protected by an additional covering layer. The resistance of the attacked bit lines is significantly increased. This technological limitation leads to an increase in the minimum achievable cell area and thus to a cost disadvantage.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an improved ROM with a vertical transistor which overcomes the above-mentioned disadvantages of the heretofore-known ROMs of this general type and which has a self-aligning programming. It is furthermore an object of the invention to provide a method of manufacturing such a ROM.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor read-only memory, comprising:
a semiconductor substrate having a main surface with a plurality of parallel trenches formed therein, each of the plurality of parallel trenches having a respective cross-sectional area and being defined by a respective base and respective side-walls opposing each other, the respective side-walls spaced apart by a trench width;
a plurality of trench crowns, each formed between a respective two of the plurality of parallel trenches;
a first plurality of bit lines, each formed in a respective one of the plurality of parallel trenches on the base;
a second plurality of bit lines, each formed on a respective one of the plurality of trench crowns;
a plurality of a word lines extending perpendicular to the first plurality of bit lines and the second plurality of bit lines;
a first, a second, and a third transistor formed in respective regions of the side-walls in a direction vertical or perpendicular to the main surface, the first and the second transistors formed on opposing sides of the side-walls and facing each other; and
an insulator filling provided in the plurality of parallel trenches, the respective cross-sectional area of each of the plurality of parallel trenches being free
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
Thomas Tom
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