Plasma damage detector and plasma damage evaluation method

Details Plasma damage detector and plasma damage evaluation method Plasma damage detector and plasma damage evaluation method

1999-03-11

2002-03-05

Bowers, Charles (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C438S018000

Reexamination Certificate

active

06353235

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a detector detecting plasma-induced damage to gate insulating films in MOS structures during the semiconductor fabrication process, and it also relates to a damage evaluation method.
2. Description of the Background Art
A recent trend toward higher-density semiconductor devices has been increasing the use of high damage processes in the fabrication of semiconductor devices. Especially plasma processes using high-energy charges have a great impact on semiconductor devices. Thus, recent studies have been directed toward damage-reduced plasma processes. At the same time, the need for a high-sensitivity plasma-induced damage detector and a method for making a low-cost, high-precision, short-time damage detection have arisen.
One of the problems with the plasma-induced impact on semiconductor devices is charging damage to gate insulating films in MOS structures.
FIGS. 5 and 6
schematically illustrate this problem.
In
FIG. 5
, a chamber CB comprises plasma producing mechanisms GN for producing plasma gas PG while holding a wafer WF by a lower electrode (not shown). The plasma gas PG produced in the chamber CB sends charges CH to the wafer WF. The charges CH react with materials on the surface of the wafer WF to apply, for example, etching to the surface. Of the charges CH, some of electrons E
1
enter into wiring, etc. formed on the surface of the wafer WF. These electrons E
1
either stay in the wafer WF, or return from the wafer WF back to the plasma gas PG, or go through the wafer WF and escape to the ground through the lower electrode (not shown).
FIG. 6
schematically shows a MOS transistor M
1
on the surface of the wafer WF in
FIG. 5
during a plasma process. The MOS transistor M
1
consists of a gate electrode G and a gate insulating film OX formed on the surface of a substrate SUB isolated by element isolation regions IR that are formed by the LOCOS method, etc., and source/drain regions S, D with impurities doped therein. On the upper surface of the gate electrode G, an interlayer insulating film (not shown) is formed and a wire IL
2
is formed on top of that. The wire IL
2
is connected to the gate electrode G by a contact hole H
1
formed in the interlayer insulating film.
On applying a plasma process to such a MOS transistor M
1
, the charge CH is sent to the vicinity of the wiring IL
2
as shown in FIG.
6
. Of the charge CH, some of electrons (E
11
, E
12
, E
13
) enter into the wire IL
2
. Here, these electrons are classified into three groups according to their entering forms, namely, electrons E
11
going through the wire IL
2
and entering directly into the contact hole H
1
; electrons E
12
entering into the wire IL
2
from the side surfaces; and electrons E
13
entering into the wire IL
2
from the upper surface. The electrons E
11
, E
12
, and E
13
try to move to the gate electrode G to flow to the substrate SUB. As a higher-density MOS transistor M
1
has a thinner gate insulating film OX, the Fowler-Nordheim tunneling current FN caused by the movement of the electrons E
11
, E
12
, and E
13
flows easily (but arrows in
FIG. 6
indicate a flow of electrons). This flow of the tunneling current FN often causes trapping of some of electrons E
11
, E
12
, and E
13
in the gate insulating film OX, generating defects in the gate insulating film OX. Depending on the degree of defects, dielectric breakdown may be developed.
Such defects are illustrated in
FIGS. 7A
to
7
C. The drawings show a cross section of a MOS transistor M
1
consisting of a gate electrode G, a gate insulating film OX, and side walls SW all formed on the P-type substrate SUB, and an N-type source electrode S and an N-type drain electrode D both formed in the substrate SUB. This MOS transistor M
1
is of N-channel type.
FIG. 7A
shows that electrons E
1
caused by plasma charging flow from the gate electrode G to the substrate SUB through the gate insulating film OX.
FIG. 7B
shows that the trapped electrons E
1
are annealed out by heat treatment. The defects in the gate insulating film OX will recover by this annealing somewhat but not completely, so that trap levels TL remain. In this state, as shown in
FIG. 7C
, the source electrode S is grounded to apply voltages Vgs, Vds and Vsub to the gate electrode G, the drain electrode D, and the substrate SUB, respectively. At this time, the electrons E
2
that migrate from the source electrode S to the drain electrode D tend to be hot carriers in the vicinity of the drain electrode D. When the hot-carrier electrons E
2
collide with atoms in the substrate SUB, producing electron-hole pairs, some of newly produced holes P
1
turn to be a substrate current Isub that flows in the direction of the voltage Vsub, and some of newly produced electrons E
3
move in the direction of the voltage Vgs to be a gate current Ig. However, the electrons E
3
are trapped in the trap levels TL in the gate insulating film OX. That is, an application of electrical stress to the N-channel MOS transistor M
1
often causes charge trapping in the gate insulating film OX in a short time. Accordingly, a repetition of such electrical stress accelerates degradation in transistor characteristics.
As a method for evaluating the degradation level of a gate insulating film deteriorated by such plasma damage, there were, for example, the CVS (Constant Voltage Stress) method and the CCS (constant Current Stress) method both utilizing a wafer with a large-area TEG (Test Element Group) having a large number of gate insulating films. The former was a method for evaluating the degradation level by examining degradation with times from the time a constant voltage is applied to a damaged gate insulating film to the time dielectric breakdown of the film occurs. The latter was a method for evaluating the degradation level by examining the amount of charge injected during a period between the application of a constant current to a damaged gate insulating film and the occurrence of dielectric breakdown of the film.
Alternatively, there were also the SPV (Surface Photo Voltage) method for evaluating degradation by measuring surface photoelectromotive force of each element to examine a potential distribution by the use of a wafer with a large-area TEG having a large number of gate insulating films, and then identifying information on the trap levels; and a method for evaluating degradation by calculating the amount of charge injection from current-voltage characteristics, using a wafer with a large-area TEG having a large number of EEPROMs (Electrical Erasable and Programmable ROM).
However, these conventional plasma damage evaluation methods utilized a TEG-equipped wafer dedicated for damage detection, and fabrication of such a dedicated wafer increases manufacturing cost. Such dedicated wafers were also not necessarily fabricated under the same conditions as a product wafer, so that the evaluation thereof would not be identical with that of the product wafer. Further, because of their low damage measuring sensitivity and long measuring time, the methods were not desirable to obtain sufficiently effective data.
As an alternative of these measuring methods, there has been developed a technique for fabricating a TEG for degradation detection of gate insulating films integrally with a product wafer in the fabrication of the product wafer, thereby obtaining the same process conditions as the product wafer and also reducing the manufacturing cost.
The Japanese Patent Laid-Open No. 10-79407A, for example, discloses a device in which through an interlayer insulating film, metal wires are densely formed on a gate electrode of an MOS capacitor formed integrally with a product wafer, and those metal wires are used as high-sensitivity plasma damage antennas; and a method utilizing the device, for evaluating a degradation level by examining the amount of charge injected until the occurrence of dielectric breakdown of insulating films in the MOS capacitor.
Another Japanese Patent Laid-Open No. 7-78829A discloses,

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