Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-23
2002-07-02
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S068000, C257S314000
Reexamination Certificate
active
06414346
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, which has a single transistor provided between embedded diffusion layers of two transistors in a memory cell so as to separate elements of the embedded diffusion layers, and a manufacturing method thereof. The present invention particularly relates to a semiconductor memory, which achieves the coexistence of the above element separation and insulating element separation, and a manufacturing method thereof.
2. Description of the Related Art
A semiconductor memory known as a representative semiconductor device is broadly divided into a volatile memory, in which stored information is erased when the power is turned off, and a nonvolatile memory, in which stored information is kept even when the power is turned off. The former is known as a random access memory (RAM) and the latter is known as a read only memory (ROM).
Of the above semiconductor memories, the ROM has been particularly adopted for a variety of information processing devices because of its nonvolatile characteristic. Above all, an EP (Erasable and Programmable) ROM and an EEP (Electrically Erasable and Programmable) ROM have been widely used. In the EPROM, written information can be erased by ultraviolet radiation and information can be electrically written again. In the EEPROM, information can be electrically erased and then written. A type of the EEPROM in which information can be erased at once and information can be written on a byte-by-bite basis has been known as a flash memory and has attracted attention as a replacement for a conventionally representative storage medium such as a floppy disk and a hard disk.
Each of these writable nonvolatile semiconductor memories has an MIS (Metal Insulator Semiconductor) structure. In this structure, a metal gate has a laminated structure having a floating gate embedded into an insulating film and a control gate being disposed above the floating gate via the insulating film. Electric charge is applied to the floating gate, which is electrically insulated from the surroundings, so as to store information. The accumulated electric charge is held in the floating gate even when the power is turned off, so that a nonvolatile function is achieved.
For example, Japanese Patent Laid-open Publication No. Hei. 6-283721 discloses the above-mentioned nonvolatile semiconductor memory, in which embedded diffusion layers are formed on semiconductor regions at both sides of a floating gate and the embedded diffusion layers are used as bit lines, and a manufacturing method thereof.
FIG. 1
is a plan view showing the structure of a conventional nonvolatile semiconductor memory disclosed in Japanese Patent Laid-open Publication No. Hei. 6-283721.
FIG. 2
is a sectional view taken along E—E line shown in FIG.
1
.
As shown in
FIGS. 1 and 2
, in the conventional nonvolatile semiconductor memory, a first floating gate
54
and a second floating gate
55
are provided in parallel with each other via a gate oxide film
53
on a region such as an active region surrounded by element separating oxide films
52
. The element separating oxide films
52
are formed at the surface of a P-type semiconductor substrate
51
. N-type drain regions
56
and
57
are formed respectively between the element separating oxide films
52
and the first and second floating gates
54
and
55
at the surface of the semiconductor substrate
51
. Further, an N-type source region
58
is formed between the first and second floating gates
54
and
55
at the surface of the semiconductor substrate
51
. A first memory transistor is composed of the first floating gate
54
, the drain region
56
, and the source region
58
, and a second memory transistor is composed of the second floating gate
55
, the drain region
57
, and the source region
58
. Namely, the source region
58
is shared by the first and second memory transistors.
The first and second floating gates
54
and
55
are covered with an insulating film
60
, which is composed of a laminated film so-called ONO (Oxide-Nitride-Oxide) including a silicon oxide film, a silicon nitride film, and a silicon oxide film. Control gates
61
are provided on the first and second floating gates
54
and
55
via the insulating film
60
. Generally, polycrystalline silicon is used as the first and second floating gates
54
and
55
and the control gates
61
.
As shown in
FIG. 1
, in the above construction of the nonvolatile semiconductor memory, the regions
56
,
57
, and
58
serve as embedded diffusion layers and extend to the adjacent memory cell as bit lines. Meanwhile, the control gates
61
extend along its length in a substantially perpendicular direction to the length of the regions
56
,
57
, and
58
, and the control gates
61
are used as word lines.
Referring to
FIGS. 3A
to
3
E, hereinafter a manufacturing method of the conventional nonvolatile semiconductor memory will be described in order of steps.
First, as shown in
FIG. 3A
, an oxidation resistance mask film
63
composed of a silicon nitride film is formed using the P-type semiconductor substrate
51
on a part serving as an active region, via a buffer film
62
composed of a silicon oxide film. Then, oxidation is performed by well-known LOCOS (Local Oxidation of Silicon) method so as to form the element separating oxide films
52
serving as field oxide films.
Next, after the buffer film
62
and the oxidation resistance mask film
63
are removed, as shown in
FIG. 3B
, normal oxidation is performed so as to form the gate oxide film
53
at the surface of the active region. Subsequently, with CVD (Chemical Vapor Deposition) method, a first conductive layer
64
made of polycrystalline silicon is entirely formed. Then, as shown in
FIG. 3C
, while resist films
65
cover regions on which the floating gates of the first conductive layer
64
are formed by photolithography method, the first conductive layer
64
is patterned so as to form the first floating gate
54
and the second floating gate
55
, which are in parallel with each other. When the first and second floating gates
54
and
55
are formed by patterning the first conductive layer
64
, mask alignment (position alignment) is performed in photolithography method. The mask alignment uses as a reference position the previously formed element separating oxide films
52
or a position alignment pattern, which is formed simultaneously with the above step.
Subsequently, an N-type impurity such as arsenic is ionically implanted into the active region by self-alignment using the resist films
65
and the first and second floating gates
54
and
55
as a mask. Afterwards, as shown in
FIG. 3D
, a heating operation is performed so as to form the N-type drain regions
56
and
57
and the source region
58
. The regions
56
,
57
, and
58
are used as embedded diffusion layers. And then, oxidation is performed after the heating operation so as to increasingly oxidize the surfaces of the regions
56
,
57
, and
58
, where N-type impurities are doped in a high concentration. Thus, an oxide film
66
is formed with a larger thickness than the gate oxide film
53
. Therefore, the drain regions
56
and
57
and the source region
58
are embedded by the oxide film
66
and are used as embedded diffusion layers.
Next, as shown in
FIG. 3E
, with CVD method, the insulating film
60
composed of an ONO film is formed for covering the floating gates and covers the first and second floating gates
54
and
55
. Afterwards, a second conductive layer
67
made of polycrystalline silicon is entirely formed thereon with CVD method, and the second conductive layer
67
is patterned so as to form the control gate
61
, thereby completing the nonvolatile semiconductor memory shown in
FIGS. 1 and 2
.
Incidentally, in the manufacturing method of the conventional nonvolatile semiconductor memory disclosed in the above publication, when forming the floating gates by patterning the conductive layer, it is inevitable that displacement (misalignment)
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