One-chip microcomputer

Details One-chip microcomputer One-chip microcomputer

1999-12-09

2002-07-09

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S210130

Reexamination Certificate

active

06418055

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a one-chip microcomputer incorporating a nonvolatile memory (for example, a flash memory) which enables electrical erasing.
FIG. 8
is a cell diagram showing a programmed state of a usual split gate nonvolatile memory. The reference numeral
1
denotes a control gate,
2
denotes a floating gate,
3
denotes a drain, and
4
denotes a source. The floating gate
2
is formed on a gate oxide film which is formed on a semiconductor substrate, and a tunnel oxide film is formed to be integrated with the gate oxide film so as to cover the floating gate
2
. The control gate
1
is formed on the tunnel oxide film.
When the nonvolatile memory of
FIG. 8
is to be set to the programmed state (i.e. programming mode), for example, voltages of 2 volts, 0 volt, and 12 volts are applied to the control gate
1
, the drain
3
, and the source
4
, respectively.
The control gate
1
is capacitive coupled to the floating gate
2
, and the floating gate
2
is capacitive coupled to the source
4
((capacitance between the control gate
1
and the floating gate
2
) <<(capacitance between the floating gate
2
and the source
4
)). Although no voltage is applied to the floating gate
2
, therefore, the state of the floating gate is set to be equivalent to that where a high voltage of, for example, 11 volts is applied to the floating gate, by the capacitive coupling ratio.
As a result, a channel in that electrons are continuously arranged is formed between the drain
3
and the source
4
, and hot electrons in the channel are injected into the floating gate
2
through the gate oxide film, so that the floating gate
2
is negatively charged. This state is the programmed state of the nonvolatile memory.
FIG. 9
is a cell diagram showing a reading state of a nonvolatile memory which is in the programmed state, and
FIG. 10
is a cell diagram showing a reading state of a nonvolatile memory which is not in the program state.
In both the nonvolatile memories of
FIGS. 9 and 10
, when the reading state is to be set, for example, voltages of 5 volts, 2 volts, and 0 volt are applied to the control gate
1
, the drain
3
, and the source
4
, respectively. In the case of
FIG. 9
, since electrons are injected into the floating gate
2
, a channel is not formed between the drain
3
and the source
4
, so that the nonvolatile memory cell is turned off.
By contrast, in the case of
FIG. 10
, since no electron exists in the floating gate
2
, a channel is formed between the drain
3
and the source
4
, so that the nonvolatile memory cell is turned on.
FIG. 7
is a block diagram of a configuration for outputting a logical value “0” or “1” in accordance with the programmed state of a nonvolatile memory cell. The reference numeral
5
denotes a nonvolatile memory cell, and
6
denotes a sense amplifier. The sense amplifier
6
outputs a voltage value of 0 volt (logical value “0”) or a voltage value of 5 volts (logical value “1”) in accordance with a result of a comparison between an output current (also called a read current or a cell current) of the nonvolatile memory cell
5
and a reference current Iref.
When the nonvolatile memory cell
5
is in the programmed state as shown in
FIG. 9
, the sense amplifier
6
detects that the output current (read current Iw) of the nonvolatile memory
5
is smaller than the reference current Iref, and then outputs the logical value “0.”
On the other hand, when the nonvolatile memory cell
5
is not in the program state as shown in
FIG. 10
(erased state), the sense amplifier
6
detects that the output current (read current Ii) of the nonvolatile memory cell
5
is larger than the reference current Iref, and then outputs the logical value “1.”
Conventionally, the output current (read current Ii) in the case where the memory cell
5
is not in the program state (erased state) is gradually reduced from the initial value of 100 &mgr;A by repeating rewriting of data, and, at the timing when the output current is reduced to 30% of the initial value, e.g. 30 &mgr;A (or the reference current Iref), the number of data rewritings (T
1
) is deemed to reach its limit. The operation life of the memory cell is judged to terminate at the timing (see FIG.
12
). As shown in
FIG. 12
, Iw is substantially constant irrespective of the number of data rewritings.
FIG. 11
is a cell diagram showing the erasing state of the nonvolatile memory. For example, a voltage of 14 volts is applied to the control gate
1
, and a voltage of 0 volt is applied to the drain
3
and the source
4
.
Then, F-N tunneling (Fowler-Nordheim tunneling) occurs so that the electrons which have been injected into the floating gate
2
are moved into the control gate
1
via the tunnel oxide film. Since the drain
3
and the source
4
have the same potential, a channel is not formed therebetween. This is the erase state of the nonvolatile memory cell.
As described above, fixed voltages are respectively applied to the control gate
1
, the drain
3
, and the source
4
for given time periods in accordance with the state of the nonvolatile memory, i.e., the programming, the reading, or the erasing.
In a one-chip microcomputer incorporating such a nonvolatile memory, when the nonvolatile memory is to be used as a ROM, the data retention characteristics play an important role.
Particularly, the memory cell
5
has the following problem. When the writing and erasing operations are repeatedly conducted, an electron trap is formed in the tunnel oxide film interposed between the floating gate
2
and the control gate
1
, by stress applied to the tunnel oxide film.
The electron trap functions as a barrier to impede the movement of electrons from the floating gate
2
to the control gate
1
(in the direction of the arrow in FIG.
11
), thereby producing a problem in that the operational life of the nonvolatile memory cell
5
is restricted.
With respect to the limit, as described above, the operational life of the nonvolatile memory cell
5
is deemed to terminate at the timing when the output current (read current Ii) in the case where the memory cell
5
is not in the program state (or is in the erase state) is reduced to 30% of the initial value of 100 &mgr;A, or to 30 &mgr;A.
SUMMARY OF THE INVENTION
Therefore, it is an object of the invention to provide a one-chip microcomputer in which preset conditions for the erasing operation can be changed in order to extend the operational life of a memory cell where data are erased by using F-N tunneling. It is another object of the invention to provide a one-chip microcomputer in which a reference level of a reading operation of a sense amplifier can be controlled in order to extend the operational life of a memory cell where data are erased by using F-N tunneling.
The invention has been conducted in order to solve the problems. The one-chip microcomputer of the invention is a one-chip microcomputer that incorporates a nonvolatile memory in which data can be electrically erased and data can be written and read, as a program memory, and is characterized in that a reference nonvolatile memory group
40
which is lower in characteristic than a nonvolatile memory
7
in a memory cell array is disposed, and, on the basis of a result of reference of the reference nonvolatile memory group
40
, the erase voltage or the erase time which is previously stored in a specific address region of the nonvolatile memory
7
is changed by a control circuit
44
.
The one-chip microcomputer of the invention is characterized in that a reference nonvolatile memory group
40
which is lower in characteristic than a nonvolatile memory
7
in a memory cell array is disposed, and, on the basis of a result of reference of the reference nonvolatile memory group
40
, the reference level of a reading operation of a sense amplifier which is previously stored in a specific address region of the nonvolatile memory
7
is changed by a control circuit
44
.
Furthermore, the one-chip microcomputer is characterized in that the reference nonvolati

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