Unload counter adjust logic for a receiver buffer

Details Unload counter adjust logic for a receiver buffer Unload counter adjust logic for a receiver buffer

1999-05-25

2002-08-13

Kim, Matthew (Department: 2186)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S029000, C711S167000

Reexamination Certificate

active

06434640

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of microprocessors and computer systems and, more particularly, to receive buffer control circuitry.
2. Description of the Related Art
Generally, personal computers (PCs) and other types of computer systems have been designed around a shared bus system for accessing memory. One or more processors and one or more input/output (I/O) devices are coupled to memory through the shared bus. The I/O devices may be coupled to the shared bus through an I/O bridge which manages the transfer of information between the shared bus and the I/O devices, while processors are typically coupled directly to the shared bus or are coupled through a cache hierarchy to the shared bus.
Unfortunately, shared bus systems suffer from several drawbacks. For example, since there are multiple devices attached to the shared bus, the bus is typically operated at a relatively low frequency. The multiple attachments present a high capacitive load to a device driving a signal on the bus, and the multiple attach points present a relatively complicated transmission line model for high frequencies. Accordingly, the frequency remains low, and bandwidth available on the shared bus is similarly relatively low. The low bandwidth presents a barrier to attaching additional devices to the shared bus, as performance may be limited by available bandwidth.
Another disadvantage of the shared bus system is a lack of scalability to larger numbers of devices. As mentioned above, the amount of bandwidth is fixed (and may decrease if adding additional devices reduces the operable frequency of the bus). Once the bandwidth requirements of the devices attached to the bus (either directly or indirectly) exceeds the available bandwidth of the bus, devices will frequently be stalled when attempting access to the bus. Overall performance may be decreased.
Another problem affecting scalability of the shared bus system is the need to distribute a single synchronous clock to the devices attached to the bus. The clock signal is used to determine when to sample the bus lines for a value and when to drive the bus lines with that value. Accordingly, the amount of skew experienced by the clock signal throughout the system must be minimized, and must be accounted for in the frequency at which the bus operates.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a computer system as described herein. The computer system employs a distributed set of links between processing nodes (each processing node including at least one processor). Each link includes a clock signal which is transmitted with and in the same direction as the signals carrying information on the link. The line carrying the clock signal may be matched to the information lines, controlling skew and transport time differences to allow for high frequency operation. Since the links each carry their own clock, distributing a single clock signal throughout the system with minimum skew may be avoided.
Because the clock signals at a transmitter and a receiver may not have a common source, a receive buffer may be employed Data transmitted across the link is stored into the receive buffer responsive to the transmitter clock signal (e.g. by maintaining a load pointer controlled according to the transmitter clock), and is removed from the buffer responsive to the receiver clock signal (e.g. by maintaining an unload pointer controlled according to the receiver clock). The buffer includes sufficient entries for data to account for clock uncertainties (e.g. skew and jitter). Additionally, the receiver includes unload pointer adjust logic which monitors the transmitter clock signal and the receiver clock signal for differences (e.g. differences in frequency). The unload pointer adjust logic makes adjustments to the unload pointer to account for the differences in the clock signal, and hence to maintain integrity of the data transmitted by preventing the load and unload pointers from overrunning each other in the buffer.
Broadly speaking, an interface logic is contemplated. The interface logic includes a receive buffer, a load counter, an unload counter and an unload counter adjust logic. Coupled to receive data, the receive buffer includes a plurality of storage locations. Each of the plurality of storage locations is capable of storing the data. Coupled to the receive buffer and to receive a first clock signal, the load counter is configured to provide a first pointer which selects one of the plurality of storage locations to store the data. The load counter is further configured to modify the first pointer responsive to the first clock signal. The unload counter is coupled to the receive buffer and to receive a second clock signal, and the load counter is configured to provide a second pointer which selects one of the plurality of storage locations to transmit data out of the receive buffer. Furthermore, the unload counter is configured to modify the second pointer responsive to the second clock signal. Coupled to the unload counter and to receive the first clock signal and the second clock signal, the unload counter adjust logic is configured to modify the second pointer responsive to differences between the first and second clock signals.
Additionally, a method for operating a receive buffer is contemplated. The method includes modifying a load pointer responsive to a first clock signal, modifying an unload pointer responsive to a second clock signal, detecting differences between the first clock signal and the second clock signal, and modifying the unload pointer responsive thereto. Moreover, a computer system is contemplated. The computer system includes a first processing node and a second processing node. The first processing node includes an interface logic comprising a receive buffer, a load counter, an unload counter, and an unload counter adjust logic. The receive buffer is coupled to receive data and includes a plurality of storage locations. Each of the plurality of storage locations is capable of storing the data. Coupled to the receive buffer and to receive a first clock signal, the load counter is configured to provide a first pointer which selects one of the plurality of storage locations to store the data. The load counter is configured to modify the first pointer responsive to the first clock signal. The unload counter is coupled to the receive buffer and to receive a second clock signal, and is configured to provide a second pointer which selects one of the plurality of storage locations to transmit data out of the receive buffer. Additionally, the unload counter is configured to modify the second pointer responsive to the second clock signal. The unload counter adjust logic is coupled to the unload counter and to receive the first clock signal and the second clock signal. The unload counter adjust logic is configured to modify the second pointer responsive to differences between the first and second clock signals. The second processing node is coupled to the first processing node, and the second processing node is configured to provide the first clock signal and the data.


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