Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
1998-01-23
2002-04-16
Eng, David Y. (Department: 2155)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
Reexamination Certificate
active
06374346
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is related to coassigned application Ser. No. 09/012,813 now U.S. Pat. No. 6,182,203 filed contemporaneously herewith and incorporated herein by reference.
TECHNICAL FIELD OF THE INVENTION
This invention relates to apparatus and techniques for manipulation and generation of Boolean values and for conditioning operations in a microprocessor.
BACKGROUND OF THE INVENTION
Microprocessors, such as general purpose microprocessors, digital signal processors, and the like, typically include an arithmetic logic unit (“ALU”) and a set of registers, sometimes referred to as general purpose registers (“GPRs”), where the operands to be operated on by the ALU can be accessed by the ALU, either immediately or one or more cycles later, in an ALU operation, and where the results of ALU operations can be immediately stored in an ALU operation.
In addition to the operations of addition and subtraction, ALUs may also have the capability of performing Boolean operations, such as compare, logical OR, bitwise OR, AND, or the like. The results of such operations, Boolean values, are typically stored in a register separate from the GPRs, for example in a status register. However, the Boolean values thus stored are not as accessible to the ALU as values stored in a GPR and require several instructions to test the resulting Boolean values. In other words, more processor cycles are needed to, for example, to present such Boolean values to the ALU as an input, should it be desired to do so in order to conditionally execute a later instruction, as compared with presenting a GPR value as an input to the ALU, which is typically done in the same clock cycle in which the ALU operation is performed.
An object of the present invention is improve the way in which instruction in a microprocessor are conditionally executed.
SUMMARY OF THE INVENTION
The present invention provides a general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers (“GPRs”)and an arithmetic logic unit (“ALU”), capable of performing arithmetic operations and Boolean operations. The ALU has a first input and a second input, and an output, the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation.
In one embodiment, at least one of the GPRs capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.
A method is also provided, performed in a microprocessor having such an architecture, in which a Boolean operation is performed in the ALU to obtain thereby a Boolean value representing the result of the Boolean operation. The Boolean value is stored in a first general purpose register in the same clock cycle as that in which the Boolean operation is performed. Thereafter, an arithmetic operation is performed in the arithmetic logic unit and the result of the arithmetic operation is stored in a second general purpose register. However, the step of performing/storing is conditioned on the Boolean value stored in the first general purpose register.
These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.
REFERENCES:
patent: 3596074 (1971-07-01), Mitrofanoff et al.
patent: 3909789 (1975-09-01), Holtey et al.
patent: 4354228 (1982-10-01), Moore et al.
patent: 4513393 (1985-04-01), Edlund
patent: 4785393 (1988-11-01), Chu et al.
patent: 5072418 (1991-12-01), Boutaud et al.
patent: 5241491 (1993-08-01), Carlstedt
patent: 5257263 (1993-10-01), Bazet et al.
patent: 5331664 (1994-07-01), Desperben et al.
patent: 5331665 (1994-07-01), Busschaert et al.
patent: 5365591 (1994-11-01), Carswell
patent: 5398198 (1995-03-01), Mahant-Shetti et al.
patent: 5442577 (1995-08-01), Cohen
patent: 5450556 (1995-09-01), Slavenburg et al.
patent: 5485411 (1996-01-01), Guttag et al.
patent: 5507027 (1996-04-01), Kawamoto
patent: 5726923 (1998-03-01), Okumura et al.
patent: 5781457 (1998-07-01), Cohen et al.
patent: 5946483 (1999-08-01), Boutaud et al.
patent: 5964825 (1999-10-01), Seshan et al.
Andrew S. Tanenbaum, “Structured Computer Organization”, Prentice-Hall, p. 70, 1976.*
S. Arya, et al; An Architecture for High Instruction Level Parallelism, Proceedings Of the Twenty-Eighth Hawaii Int'l Conf. On System Sciences, vol. II, pp. 153-162.*
Forney, G. David Jr., The Viterbi Algorithm, Proceedings of the IEEE, vol. 61, No. 3, Mar. 1973, pp. 268-278.
Texas InstrumentsTMS390S10 MicroSPARC Reference Guide,1992, pp. 1-158.
Gwennap, Linley, Mitsubishi Designs DVD Decoder, Microprocessor Report, vol. 10, No. 16, Dec. 9, 1996, pp. 5-9.
Case, Brian, First Trimedia Chip Boards PCI Bus, Microprocessor Report, vol. 9, No. 15, Nov. 13, 1995, pp. 2-7.
Texas InstrumentsTMS470R1x 32-Bit Microcontroller Family User's Guide.
Gwennap, Linley, Intel, HP Make EPIC Disclosure, Microprocessor Report, vol. 11, No. 14, Oct. 27, 1997, pp. 5-9.
Davis Alan L.
Seshan Natarajan
Simar, Jr. Laurence R.
Tatge Reid E.
Brady III W. James
Eng David Y.
Laws Gerald E.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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