Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-04-04
1998-04-07
Kim, Matthew M.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711152, 711 3, G06F 1208
Patent
active
057377588
ABSTRACT:
An efficient method for handling multiple conflicting snoop requests with minimal stalling on the external bus by using blocking conditions to maintain and update a snoop queue for maintaining cache coherence in a computer system with caching units. An entry in a snoop queue is allocated to a snoopable request which has an associated snoop address. The snoop address is compared with addresses corresponding to previously allocated entries stored in the snoop queue. A block condition is set if there is a match between the snoop address and one or more of the addresses stored in the snoop queue. One or more history bits are set in the snoop queue indicating a chronological ordering of the entry in the snoop queue. A snoop operation corresponding to the snoop request is blocked until the block condition is cleared.
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Intel Corporation
Kim Matthew M.
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