Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-12-10
2002-08-27
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06442744
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for improving auto-placement of circuit elements such as cells and transistors in semiconductor integrated circuit design, a storage medium having a program for executing the method and a fabrication method of a semiconductor device using the method.
2. Description of the Related Art
In a design stage of a semiconductor integrated circuit, circuit elements thereof are automatically placed on a chip design plan by a computer on the basis of a net list. For example, in auto-placement according to a min-cut method, placement of elements is determined in the following way: a chip design plan is divided into two regions by a cut line to distribute the circuit elements into two groups on both sides of the cut line so that the number of interconnecting lines traversing the cut line is minimized, the two regions are each further divided by a cut line under the same condition and such a process is repeated until one element is included in a divided region. In another prior art auto-placement, not only the number of interconnecting lines traversing the cut line, but also areas of elements stored in a cell library, are taken into consideration, and the sums of areas of elements in the respective two regions divided as above are calculated to obtain a difference between the sums, and the elements are placed as above so that the difference does not exceed a set value.
However, as the scale of a semiconductor integrated circuit has been larger, wiring congestion has been increased, which in turn, has caused a longer wiring length. Since a ratio of a wiring delay due to wiring resistance and capacitance to a gate delay is increased by miniaturization of circuit elements, there is a demand on reduction in wiring length by decreasing a degree of wiring congestion.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method and apparatus for improving auto-placement to enable wiring length to be shortened, a storage medium having a program for executing the method and a fabrication method of a semiconductor device using the method.
In the present invention, there is provided a method of improving an auto-placement by a computer, the auto-placement being performed by placing circuit elements on a design plan based on a net list, comprising the steps of: (1) classifying nets into such groups after the auto-placement that nets of each group have logically equivalent signal; and (2) exchanging input terminals between different nets in a group so as to shorten a wiring length.
With the present invention, a wiring length is shortened and wiring congestion is decreased as a result.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.
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Arent Fox Kintner Plotkin & Kahn
Dinh Paul
Fujitsu Limited
Smith Matthew
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