Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
1999-03-31
2002-08-13
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C710S046000, C710S047000, C710S048000, C710S054000, C710S055000, C710S062000, C710S263000
Reexamination Certificate
active
06434630
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a computer system. Specifically, the present invention relates to a host adapter which reduces the number of input/output (I/O) completion interrupts generated from the host adapter to a host microprocessor.
2. Brief Description of the Related Art
In a computer system, a host microprocessor (host system) or central processing unit (CPU) retrieves information from a number of peripheral I/O devices, such as disk drives, by sending an I/O request to an I/O controller or adapter. The I/O controller processes the I/O requests intended for the peripheral I/O devices. Most I/O controllers can simultaneously handle multiple I/O requests from the host microprocessor. The I/O controller processes several low-level commands associated with each I/O request. For example, for I/O devices attached to a small computer system interface (SCSI) bus, a single I/O request may include commands to arbitrate for the SCSI bus, commands to select the target I/O device, commands to request data transfer, commands to disconnect and reconnect the I/O device from the SCSI bus, and other commands to change the SCSI bus state.
In previous computer systems, after an I/O device completes an I/O request or one of the low-level commands, the I/O controller notifies the host microprocessor through a hardware interrupt. The interrupt causes the host microprocessor to determine which I/O request was completed and whether the I/O request was correctly executed. The host microprocessor must suspend other operations in order to service the interrupt from the I/O controller. Also, when the host microprocessor services each interrupt, the host microprocessor incurs an overhead or burden. The overhead is caused by the interrupt as it enters and exits the host microprocessor.
If the host microprocessor sends a large number of I/O requests, i.e., the I/O workload is high, then the host microprocessor receives a corresponding large number of interrupts, resulting in a significant amount of overhead associated with the interrupts. In a multi-user or multi-tasking computer system, this overhead decreases the amount of host microprocessor time and resources (e.g., power) available to process other applications. This results in a slowdown in system performance. As existing host microprocessors are designed to be faster, the slowdown in system performance due to the host servicing interrupts is even more noticeable.
Over the years, in addition to faster host microprocessors, the speed of peripheral I/O devices in processing I/O requests has also improved. This increased speed has increased the frequency of I/O completion interrupts to the host microprocessor.
In addition, program applications running on the host microprocessor have demanded greater processing power. Thus, there has been a greater demand for the processing power used to accomplish I/O requests and responses.
SUMMARY OF THE INVENTION
The present invention relates to a host adapter which uses an adaptive method to combine I/O request completion reports and to significantly reduce the number of interrupts to a host microprocessor. Specifically, the adapter significantly increases the ratio of I/O completion reports per second (IOPS) to interrupts.
By combining successful I/O completion reports and reducing the number of interrupts, the host adapter reduces the overhead incurred in servicing interrupts for successfully completed I/O requests. This reduces the amount of processing time (‘I/O bound’ time) and power spent by the host microprocessor in processing interrupts from the adapter, and creates more time and power for the host microprocessor to process user applications. In one embodiment of the present invention, the amount of time and/or resources (e.g., power) spent by the host microprocessor in servicing interrupts (CPU utilization) is decreased by 20%.
One advantage of one embodiment of the present invention is that it adapts to the I/O request workload of the host microprocessor. The busier the host microprocessor, the more I/O completion reports are returned by the adapter with a single interrupt. Specifically, the higher the I/O request workload, the higher the ratio of I/O completion reports per second (IOPS) to interrupts. For example, in one embodiment, if the workload is relatively low, e.g., only 5-10 I/O requests are generated at a time, then 3-5 I/O completion reports may be reported with a single interrupt to the host microprocessor. If the workload is relatively high, e.g., 30-60 I/O requests are generated at one time, then up to 30 I/O completion reports may be reported with a single interrupt to the host microprocessor. This provides a significant advantage because the busier the host microprocessor is, the less the host microprocessor can afford the time and resources to service interrupts and the overhead associated with interrupts.
In addition to reducing the number of interrupts to the host, another advantage of the adapter is that it maintains sufficient work for the I/O devices by starting a timer when an I/O device has no more I/O requests left to process, i.e., when an I/O device becomes ‘idle.’ When the timer expires, all successfully completed but unreported I/O requests from all I/O devices are posted to the host microprocessor with an interrupt. In some host applications, the host microprocessor will wait for I/O requests to be completed and reported before sending out more I/O requests. After processing these completed I/O requests, the host microprocessor may send new I/O requests to the I/O devices. This increases the likelihood that one or more new I/O requests will be sent to the I/O device which is idle. As a result, the adapter decreases latency and improves overall performance of the computer system.
Another advantage of the present invention is that one embodiment adapts to the number of I/O devices which are active at a given time. If several I/O devices are active, then a threshold value to trigger an interrupt is high. A high threshold value reduces the number of interrupts per second (IPS) and increases the number of reported I/O completions per interrupt.
Due to the adaptive nature of the present invention, it improves system performance regardless of the I/O request workload (either a high workload or a low workload), the type of access (either sequential or random access), the type of system configuration, the number of I/O devices, the type of I/O requests, and either queued or non-queued I/O requests.
One aspect of the present invention relates to a method of processing dispatched I/O requests in a computer system, in which a host microprocessor of a host computer dispatches I/O requests to an I/O controller to initiate transfers of data between the host computer and a plurality of peripheral I/O devices. The method of processing dispatched I/O requests comprises (a) processing the dispatched I/O requests by transferring data between the peripheral I/O devices and a memory of the host computer; (b) concurrently with act (a), determining, based at least upon a number of unreported completed I/O requests and a number of pending I/O requests, whether to interrupt the host microprocessor; (c) when it is determined in act (b) that the host microprocessor is to be interrupted, interrupting the host microprocessor and reporting to the host microprocessor the unreported completed I/O requests; and (d) varying the number of unreported completed I/O requests reported to the host microprocessor in act (c) according to a current workload of the I/O controller.
In one embodiment, act (b) comprises comparing the number of unreported completed I/O requests to the number of pending I/O requests. In one configuration, the method comprises interrupting the host microprocessor when the number of unreported completed I/O requests is greater than or equal to the number of pending I/O requests.
In one embodiment, act (b) of determining whether to interrupt the host microprocessor is further based on the number of pending I/O requests tha
Micalizzi, Jr. Charles
Nghiem Thanh X.
Nguyen Toan B.
Romaniec Richard L.
Gaffin Jeffrey
Knobbe Martens Olson & Bear LLP
Perveen Rehana
QLogic Corporation
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