Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-04
2002-05-21
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S335000, C257S336000
Reexamination Certificate
active
06392274
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the structure of a high-voltage metal-oxide-semiconductor (HVMOS) transistor and the method of making the same. More particularly, the invention relates to the structure of, and method of making, an HVMOS transistor that reduces snapback.
2. Description of the Prior Art
High-voltage metal-oxide-semiconductor (HVMOS) transistors are in wide use in many electric devices, such as CPU power supplies, power management systems, AC/DC converters, etc. Consequently, improving their operating characteristics is of considerable importance to electronics manufacturers.
Please refer to FIG.
1
.
FIG. 1
is cross-sectional diagram of an HVMOS transistor
30
according to the prior art. As shown in
FIG. 1
, the HVMOS transistor
30
is manufactured on a semiconductor wafer
10
. The semiconductor wafer
10
comprises a P-type silicon substrate
11
and a P-type epitaxial layer
12
formed on the surface of the P-type silicon substrate
11
. The HVMOS transistor
30
comprises a P-well region
21
formed in the P-type epitaxial layer
12
, an N-type source
22
formed within the P-well region
21
, an N-type drain
24
formed in the P-type epitaxial layer
12
, and a gate
14
.
When a voltage is applied to the drain
24
, a depletion region, or a space-charge region that is depleted of holes and electrons but contains positively ionized donor atoms on one side and negatively ionized acceptor atoms on the other side, occurs. As the voltage applied to the drain
24
increases, both the width of the depletion region and the electric field in the region increase. When an electron in the depletion region is accelerated by the strong electric field caused by a large reverse bias, the electron, well-known as a hot electron, gains kinetic energy that is equal to, or greater than, the band gap energy of silicon. The hot electron collides with the lattice and breaks a covalent bond. The breaking of a covalent bond, which is equal to the elevation of an electron from the valence band to the conduction band, results in the generation of an electron-hole pair.
The two electrons, the original one and the one resulting from the collision, are in turn accelerated by the high electric field, gain kinetic energy greater than the gap energy, collide with the lattice, and generate two additional electron-hole pairs. These additional electrons will create more electrons in a chain reaction known as the carrier multiplication effect, and finally cause an avalanche breakdown resulting from impact ionization. The avalanche process of carrier generation by collision results in a very large number of carriers, and hence a large increase in the current.
Both electrons and holes take part in impact ionization. When the drain voltage is large, a substantial hole current I
sub
can flow to the substrate, and the product of I
sub
and the substrate resistance R
sub
, i.e. the inductive voltage V
b
, becomes large enough to forward-bias the source-substrate junction, causing electron injection into the substrate. This injection leads to a parasitic n-p-n (source-substrate-drain) bipolar transistor
40
effect.
The parasitic bipolar transistor
40
presents the problem of snapback. Snapback occurs when the parasitic bipolar transistor
40
is turned on by the large impact ionization hole current from the drain before the substrate-drain diode breaks down. When snapback occurs, the drain current increases very rapidly with only a miniscule voltage, causing damage to the HVMOS transistor. The minimum drain voltage at which snapback occurs, called the snapback voltage, decreases as the drain-substrate electric field increases. In addition, the channel conductance of the HVMOS transistor
30
according to the prior art method is insufficient and thus results in inferior current drifting capabilities.
SUMMARY OF THE INVENTION
It is therefore a primary objective of this invention to provide an improved structure of an HVMOS transistor to reduce the parasitic n-p-n bipolar transistor phenomenon, thereby alleviating snapback effects.
According to this invention, the HVMOS transistor is manufactured on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate of a first conductivity type and an epitaxial layer of a second conductivity type formed on the surface of the silicon substrate. The HVMOS transistor comprises a first well region of the second conductivity type formed within the epitaxial layer, a second well region of the second conductivity type formed within the first well region, a source region of the first conductivity type formed within the second well region of the epitaxial layer, a drain region of the first conductivity type formed in the epitaxial layer, a gate located between the source region and the drain region on the surface of the epitaxial layer, and a diffused region of the second conductivity type formed both in the epitaxial layer and in the silicon substrate. The diffused region of the second conductivity type is under the first well region and overlaps the first well region.
According to one aspect of this invention, the structure of the HVMOS transistor provides a stronger lateral electric field along the channel resulting from the second well region of the second conductivity type, which results in higher channel conductance and better current drifting capabilities. Moreover, to reduce parasitic transistor effects, the resistance of the substrate R
sub
is minimized using the diffused region of the second conductivity type, which is under the first well region and overlaps with the first well region, ensuring that the inductive voltage V
b
remains smaller than the snapback voltage.
REFERENCES:
patent: 4007478 (1977-02-01), Yagi
patent: 4409606 (1983-10-01), Wagenaar et al.
patent: 4639761 (1987-01-01), Singer et al.
patent: 5256893 (1993-10-01), Yasuoka
patent: 5428241 (1995-06-01), Terashima
patent: 5844275 (1998-12-01), Kitamura et al.
patent: 5977590 (1999-11-01), Suzuki
patent: 6194760 (2001-02-01), Lee
patent: 6194761 (2001-02-01), Chiozzi et al.
patent: 3-57-211778 (1982-12-01), None
Eckert II George C.
Hsu Winston
Lee Eddie
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