Semiconductor device

Details Semiconductor device Semiconductor device

1999-08-27

2002-04-23

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S298000, C257S379000, C257S532000, C326S083000, C326S093000, C326S103000, C365S185100

Reexamination Certificate

active

06376869

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device which captures data in synchronization with a strobe signal.
2. Description of the Related Art
FIG. 1
shows a configuration example of a semiconductor device according to a conventional technique. Specifically,
FIG. 1
shows a configuration of a memory system which uses, for example, an SDRAM (Synchronous Dynamic Random Access Memory) as a memory module, and is controlled by a controller. In addition, the memory system operates in synchronization with a clock signal. As shown in the figure, a plurality of memory modules
10
,
11
, . . . are connected to the controller
30
by bus lines such as a command bus
21
, a data strobe (DQS) bus
22
, a data mask (DM) bus
23
, a data (DQ) bus
24
and a clock bus
25
. Additionally, a clock source
40
supplies a clock signal to the controller
30
. The memory module is a single memory chip or a plurality of memory chips. In this configuration, a data read/write operation is carried out in synchronization with a rising edge or a falling edge of the clock signal which is supplied from the clock source
40
. This method is called DDR (Double Data Rate).
FIG. 2
is a timing chart showing a write operation of the above-mentioned memory system. A write command is fixed at the rising edge of the clock signal CLK (point A). Then, the controller
30
outputs the data strobe signal DQS, the data mask signal DM and the data signal DQ to each memory module in synchronization with the clock signal CLK. Each memory module captures the data mask signal DM and the data signal DQ at the rising edge and the falling edge of the data strobe signal DQS. When a high-level data mask signal DM is captured at the rising edge or the falling edge of the data strobe signal DQS, a corresponding data signal DQ, being shown as (D
2
) in
FIG. 2
, is masked.
FIG. 3
is a timing chart showing a read operation. A read command is fixed at the rising edge of the clock signal CLK (point B). Then, each memory module outputs the data strobe signal DQS, and the data signal DQ to the controller
30
in synchronization with the clock signal CLK. The controller
30
captures the data signal DQ in synchronization with a signal delayed from the rising edge and the falling edge of the data strobe signal DQS.
As mentioned above, the memory system uses the data strobe (DQS) bus
22
bidirectionally such that the sending directions of the data strobe signal DQS and the data signal DQ are the same. In addition, the memory system is configured such that lengths of each bus line between the controller
30
and each memory module are the same. Thus, skew in signals which are exchanged between each memory module and the controller
30
at the time of the data read/write operation is reduced.
The data strobe signal DQS and the data signal DQ are sent bidirectionally between the controller
30
and the memory module according to a read/write operation mode. On the other hand, the data mask signal DM is sent from the controller
30
to each memory module only at the time of the write operation. Therefore, each of a DQS terminal and a DQ terminal in the memory module functions as an input/output circuit, and the DM terminal functions as an input circuit.
FIG. 4A
is a diagram showing an example of the DQS terminal or the DQ terminal (represented as DQS/DQ terminal hereinafter) in the conventional memory module.
FIG. 4B
is a diagram showing an example of the DM terminal in the conventional memory module. As shown in
FIG. 4A
, each of the DQS/DQ terminal includes a pad
50
, an output buffer
52
and an input buffer
54
. The DQS/DQ terminal is connected to the above-mentioned bus line through the pad
50
, and the output buffer
52
and the input buffer
54
are connected in parallel. The output buffer
52
is configured by a PMOS (P-channel Metal Oxide Semiconductor) transistor
56
and an NMOS (N-channel Metal Oxide Semiconductor) transistor
58
. As shown in
FIG. 4B
, the DM terminal includes a pad
60
and an input buffer
62
. The DM terminal is connected to the bus line through the pad
60
. Accordingly, the terminal capacity of the DM terminal is less than the terminal capacity of the DQS/DQ terminal at the time of the write operation, that is, when data is input to the memory module.
However, since the terminal capacity of the DM terminal is different from that of the DQS/DQ terminal, there is the following problem. The problem will be described with reference to
FIGS. 5A and 5B
.
FIG. 5A
shows a conventional memory system and
FIG. 5B
shows signal waveforms of signals in the configuration.
As shown in
FIG. 5A
, each of memory modules
70
-
72
is connected to a controller
75
by a bus lines
73
. In addition, the memory system is connected to a clock source, which is not shown in the figure. The controller
75
outputs a data strobe signal DQS (a DQS signal), a data signal DO (a DO signal) and a data mask signal DM (a DM signal) at the time of write operation in synchronization with a clock signal CLK (a CLK signal). These signals are sent to the memory modules through the bus lines.
FIG. 5B
shows the waveforms in the configuration at the time of the write operation. Signals of DQS, DM and DQ travel from the controller
75
to the memory modules
70
-
72
. The reference number of each waveform in
FIG. 5B
corresponds to the reference number in FIG.
5
A. For example, a DOS signal at a point
1
in
FIG. 5A
takes a DQS waveform indicated by
1
in FIG.
5
B. In
FIG. 5B
, V
ref
represents a reference voltage.
As shown in
FIG. 5B
, the difference between the slopes of the rising/falling edge of the signals is small, at the point
1
in FIG.
5
A. At this time, the setup time
1
is equal to the hold time
1
for both of the DQ signal and the DM signal. The setup time
1
means the setup time at the point
1
. It is the same for other points.
As mentioned before, the terminal capacity of the DQS/DQ terminal in each memory module is larger than that of the DM terminal. Thus, as a signal travels from the point
1
to the point
4
, the rising/falling edge of the DQS/DQ signal gradually becomes gentler than the rising/falling edge of the DM signal. The difference is apparent by comparing a waveform of the DQS/DQ signal at the point
4
with a waveform of the DM signal at the point
4
.
Since the slope of the rising/falling edge of the DQ signal is the same as that of the DQS signal at the point
4
, the setup time and the hold time can be kept adequately for the DQ signal, that is, the setup time
4
is equal to the hold time
4
. On the other hand, the slope of the rising/falling edge of the DM signal is steeper than that of the DQS signal. Therefore, the hold time becomes shorter than the setup time for the DM signal as shown in the waveform, that is, setup time
4
>hold time
4
. As a result, an adequate margin can not be kept for the hold time, thereby a stable operation becomes difficult when carrying out high-speed access.
Therefore, according to the conventional technique, there is a problem that a timing margin for data input at the time of the write operation can not be kept adequately, since the terminal capacity of the DM terminal is different from that of the DQS/DQ terminal.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device and a system including the semiconductor device which can keep an adequate timing margin for data input at the time of a write operation, the semiconductor device inputting/outputting data in synchronization with a strobe signal.
The above object of the present invention is achieved by a semiconductor device which includes a first terminal for inputting and outputting data and a second terminal for inputting control data in synchronization with a strobe signal, the semiconductor device including:
an equivalent circuit which is provided in the second terminal, having a capacitance which is equ

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