Semiconductor device with DMOS, BJT and CMOS structures

Details Semiconductor device with DMOS, BJT and CMOS structures Semiconductor device with DMOS, BJT and CMOS structures

1999-10-20

2002-05-21

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S335000, C257S336000, C257S337000, C257S338000

Reexamination Certificate

active

06392275

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device including a bipolar junction transistor (BJT), a complementary MOS (CMOS) transistor and a double diffused MOS (DMOS) transistor, and to a manufacturing method thereof.
2. Description of the Related Art
In a typical complex system for complexly performing signal processing, operations, logic and other functions, each of the functions is performed by semiconductor devices manufactured by various manufacturing processes. For instance, bipolar junction transistors (BJTs) having high transfer conductance, are usually used for an analog circuits. However, complementary MOS (CMOS) transistors having high integration and low frequency are usually used for logic or memory circuits. In particular, double diffused MOS (DMOS) transistors are usually used for circuits requiring operation at high voltages and at high switching speeds.
However, there have been disclosed various processes for manufacturing integrated circuit chips in which both CMOS devices and bipolar devices are formed, and various processes for manufacturing integrated circuit chips in which DMOS devices appropriate for operation at high voltages are formed. Here, the integration of the device is increased; however, the manufacturing process is complex due to the multiple mask layers required for the manufacturing process, and there are limits on the performance of each of the devices. A DMOS device will be described with reference to the attached drawings.
FIG. 1
is a schematic sectional view of a conventional lateral DMOS transistor, and
FIG. 2
is an enlarged view of portion A of FIG.
1
.
Referring to
FIGS. 1 and 2
, an n-type well region
2
is formed in a p-type semiconductor substrate
1
such that the well region
2
is adjacent to a surface of the semiconductor substrate
1
. A p-type top region
3
having a predetermined length and an n-type drain region
4
are formed in the well region
2
. The length of the p-type top region
3
is determined by the voltage V
ds
between a drain and a source, and is spaced apart from the drain region
4
. A p-type body region
5
is formed in another predetermined region of the semiconductor substrate
1
, spaced apart from the well region
2
by a predetermined distance. An n-type heavily doped source region
6
and a p-type heavily doped source region
7
, which are adjacent to each other, are formed in the p-type body region
5
.
A source electrode
8
is formed to be electrically connected to the source region
6
, and a drain electrode
9
is formed to be electrically connected to the drain region
4
. Also, a gate electrode
10
is formed to be electrically insulated from the semiconductor substrate
1
by a gate insulating layer
11
. The source electrode
8
, the drain electrode
9
and the gate electrode
10
, are electrically insulated by an interdielectric layer.
The above lateral DMOS transistor is turned on or off according to a signal applied to the gate electrode
10
in the state in which a high voltage is applied to the drain electrode
9
. Particularly, when the lateral DMOS transistor is used as a power switching device at a high voltage, e.g., 600~800V and the device is in the on-state, electrons move to the drain region
4
from the source region
6
, and energy is stored in an inductor connected to an external circuit. When the device is in the off-state, charges stored in the inductor are discharged, and the discharged current flows to the source electrode
8
through a resistance R
b
(of
FIG. 2
) in the body region
5
. When the voltage is dropped by the resistance R
b
, and the junction of the body region
5
and the source region
6
is forward-biased by the voltage drop, a parasitic npn BJT
20
(of
FIG. 2
) formed by the n-type well region
2
, the p-type body region
5
and the n-type source region
6
operates. When the parasitic npn BJT
20
operates, the device cannot be controlled by the gate electrode
10
any more, and further, the device may be broken.
There have been proposed various methods for suppressing turn-on of the parasitic npn BJT
20
, where a method for reducing the size of resistance R
b
in the body region
5
has been studied.
Meanwhile, the breakdown voltage must be increased to use the lateral DMOS transistor at a high voltage. A depletion layer must be extended in the direction of the semiconductor substrate
1
in the well region
2
to realize a high breakdown voltage of 600V or more, and thus a lightly doped p-type semiconductor substrate must be used such that the resistivity becomes approximately 100 &OHgr;cm. However, if an NMOS transistor is formed on the lightly doped semiconductor substrate, punchthrough easily occurs in a channel having a length of approximately 3 &mgr;m or less, to thereby reduce the breakdown voltage between the drain and the source. Also, if the npn BJT is formed on the semiconductor substrate, an intrinsic base region of the npn BJT is formed with a concentration the same as that of the body region of the DMOS transistor, to thereby deteriorate characteristics of the npn BJT and DC current gain h
FE
due to the lightly doped base region.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a semiconductor device having a substrate in which a BJT, a CMOS transistor and a DMOS transistor are formed.
It is another objective of the present invention to provide a method for manufacturing the semiconductor device.
Accordingly, to achieve the first objective, a semiconductor device according to an embodiment of the present invention includes a bipolar junction transistor and a DMOS transistor formed on a semiconductor substrate of a first conductivity type. The DMOS transistor comprises a body region of the first conductivity type and a well region of a second conductivity type formed in a predetermined upper region of the semiconductor substrate, wherein the body region and the well region are spaced by a predetermined interval, a highly-doped bottom layer of the first conductivity type to contact the lower surface of the body region in the semiconductor substrate, a highly-doped source region of the second conductivity type formed in a predetermined upper region of the body region, a highly-doped drain region of a second conductivity type formed in a predetermined upper region of the well region, a gate electrode formed on a channel formation region of the body region wherein an insulating layer is interposed between the gate electrode and the body region, a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region.
Here, preferably, the semiconductor device further comprises a top region of the first conductivity type formed in an upper portion of the well region.
Preferably, the bipolar junction transistor comprises a well region of the first conductivity type formed in a predetermined upper portion of the semiconductor substrate, a highly-doped bottom layer of the first conductivity type formed in a predetermined region of the well region, a first base region of the first conductivity type contacting the upper surface of the bottom layer in the well region, a highly-doped second base region of the first conductivity type contacting the upper portion of the bottom layer in the first base region, a highly-doped emitter region of the second conductivity type formed in a part of the surface of the first base region, and a base electrode, an emitter electrode and a collector electrode electrically connected to the second base region, the emitter region and the collector region, respectively;
To achieve the first object, a semiconductor device according to another embodiment of the present invention includes a MOS transistor and a DMOS transistor formed on a substrate of a first conductivity type. Here, the DMOS transistor comprises a body region of the first conductivity type and a well region of a second c

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